Altera is committed to providing intellectual property (IP) cores that work seamlessly with Altera® tools or interface specifications, providing a complete system-on-chip (SoC) solution quickly and easily. Altera may award IP cores one or more of the following certifications.
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| Altera awards the AMPPSM Approved certification to all third-party IP cores that have undergone Altera's thorough internal review process. Altera works closely with AMPP Partners to ensure that these cores support the newest device families, integrate with Altera design software, and enable a high-quality user experience. Refer to the AMPP Program web page for more information. | ||
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Altera awards the Qsys Compliant certification to IP cores that seamlessly integrate with the Qsys system integration tool included in the Quartus® II software. Qsys Compliant cores support the interconnect which leverages the Avalon® Streaming and Memory-Mapped interfaces. View the online IP catalog to see which Altera and partner IP cores are Qsys Compliant. |
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Altera awards the SOPC Builder Ready certification to IP cores that have plug-and-play integration with SOPC Builder, part of Quartus II software. SOPC Builder Ready cores support Avalon interfaces to communicate with the Nios® II embedded processors, as well as other data masters, via the system interconnect fabric. These cores also include applicable software drivers, low-level routines, or other software design files. Refer to the SOPC Builder Ready web page for more information about SOPC Builder Ready IP cores.
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| Altera awards I-Tested certification to IP cores that have been tested to be compliant with protocol standards. These cores are verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the necessary protocols. Refer to the I-Tested web page for more information about I-Tested IP cores. |
