SDLC Controller
The CAST SDLC controller is a high-speed synchronous serial communication interface megafunction.
Overview
The CAST synchronous data link communication (SDLC) controller's operation is similar to that used in the Intel 8XC152 global serial channel (GSC) working in SDLC mode under the control of the CPU. Special function registers and three interrupt sources facilitate communication with the CPU. This feature allows the SDLC controller to be easily integrated into any CPU megafunction.
The design is strictly synchronous with positive-edge clocking, has no internal tri-states, and has a synchronous reset.
Features
- Based on the 8XC152 GSC
- Single- and double-byte address recognition
- 16-bit & 32-bit frame check sequence
- Non-return-to-zero (NRZ) & non-return to zero inverted (NRZI) data encoding
- Automatic bit stuffing & stripping
- Three-byte-deep receive & transmit first-in first-out buffers (FIFOs)
- Full- or half-duplex operation
- Variable baud rate
- External or internal transmit/receive clock
Block Diagram
Figure 1. The Block Diagram for the SDLC Controller Megafunction
Device Utilization & Performance
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Availability |
| LEs(1) |
Memory |
| ACEX® 1K30 |
-1 |
854 |
- |
117 MHz |
Now |
| APEX™ 20K30E |
-1 |
839 |
- |
118 MHz |
Now |
| APEX™ II 2A15 |
-7 |
841 |
- |
132 MHz |
Now |
| Cyclone™ 1C3 |
-6 |
784 |
- |
194 MHz |
Now |
| Stratix™ 1S10 |
-5 |
785 |
- |
214 MHz |
Now |
| Stratix™ II 2S15 |
-3 |
747 |
- |
277 MHz |
Now |
Notes:
- LE = logic elements; the LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
Deliverables
Encrypted Licenses
- Post-synthesis Altera® hardware description language (AHDL) or EDIF
- Assignment & configuration
- Symbol file
- Include file
- Sample design
- Vectors for testing the functionality of the megafunction
HDL Source Licenses
- VHDL or Verilog register transfer level (RTL) source code
- Testbench
- Vectors for testbench
- Expected results for testbench
- Simulation and synthesis scripts
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
URL: www.cast-inc.com
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