10 Gigabit Fibre Channel FC-1 Core
Features
- Complies with the American National Standards Institute (ANSI) T11 10-GFC (Gigabit Fibre Channel) Rev. 3.0 specification
- Includes optional media-independent 64-bit, non-double data rate (DDR) interface or standard 32-bit, 10-Gbit medium independent interface (XGMII) DDR interface to connect to FC-2 and higher layers
- Includes optional 10-Gbit attachment unit interface (XAUI) interface implemented with embedded quad serializer/deserializer (SERDES), which provides an efficient board-level interface to optical modules and loopback
- Implements 4-to-1, 10-Gbit 16-bit interface (XSBI) multiplexer/de-multiplexer when selected technology is Altera® CPLD to connect to FC-0 physical layers
- Implements a 10-GFC data scrambler which generates transition-rich signals to the application high-speed optical link and data descrambler on the core receive path
- Features a 64- and 66-bit data coder/decoder (CODEC) with synchronization header insertion or deletion on respective transmit or receive
- Performs 66-bit block synchronization on the PCS receive path and 66-bit block encoding on transmit with gearbox function
- Includes 64- to 66-bit encoder-decoder performing 66-bit word alignment, the 64- to 66-bit receive path decoding, the 64- or 66-bit transmit path encoding, and the 64- to 66-bit transmit path conversion for block overhead bits
- Implements XGMII-XSBI clock rate decoupling with elastic buffers on the transmit and receive paths
- Provides rate-matching first-in first-out (FIFO) with idle insertion-and-removal in receive direction, simplifying system clock distribution
- Performs programmable loopback on the core XGMII interface available for application test
- Implements test pattern generator-checker for link testing and in-system testing
- Implements bit error rate monitoring, with high error rate indication, which provides constant line-quality monitoring
- Helps to reduce time-to-market and provide cost-effective solutions for Altera Stratix™ CPLDs or ASIC implementations
- Contains complete design kit which includes frame generators and checking models, standard compliance scenario and implementation scripts for various ASICs, and programmable logic technologies
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. 10 Gigabit Fibre Channel FC-1 Block Diagram
Description
The 10 Gigabit Fibre Channel FC-1 core is designed for 10-Gbit fiber channel applications. It includes a line scrambler and descrambler, 64- and 66-bit encoder/decoder, test pattern generator and checker, block synchronization and gearbox, and clock and rate decoupling elastic buffers.
Designers can configure the core to implement either a XGMII or a XAUI when a design is targeted to an Altera Stratix GX CPLD. Typically, the XGMII interface is used to integrate the core with custom logic in a CPLD or an ASIC solution, while the XAUI interface provides a simpler, 16-bit board-level interface to connect the FC-1 core to a FC-2 layer device.
On the line side, the core implements a 64-bit interface which typically connects, via a SFI multiplexer/de-multiplexer, to a XSBI interface operating at 657.4 MHz. The SERDES framer interface (SFI) multiplexer/de-multiplexer is implemented with Stratix or Stratix GX high-speed LVDS I/O macros. The XSBI interface attaches directly to the transceiver module. Users can also implement a test pattern generator and checker.
The 10 Gigabit Fibre Channel FC-1 core complies with the ANSI 10GFC Rev. 3.0 standard and is updated to comply with the latest ANSI drafts and final specification.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization
Logic Elements (LEs) |
Performance
(fMAX) |
Parameter Setting |
| Stratix EP1S25 |
-6 |
6,400 |
185 MHz |
161.13 MHz |
| Stratix GX EP1SGX25 |
-6 |
6,500 |
185 MHz |
161.13 MHz |
Deliverables
Register transfer level (RTL) synthesizable VHDL and Verilog source code or encrypted netlist
- Configurable VHDL and Verilog verification testbenches
- Scripts for Mentor Graphics® LeonardoSpectrum™ synthesis tool
- Implementation script for the Quartus® II version 2.1 design software
- Detailed user guides
Contact Information
For additional information, contact:
MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld Germany
Tel: +49 81-31-333-9390 (Germany) or +1 408-273-4567 (USA)
Fax: +49 81-31-333-9391 (Germany) or +1 408-273-4667 (USA)
E-mail: info@morethanip.com
Internet: http://www.morethanip.com
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