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Altera CPRI IP

Home > Products > Intellectual Property > Communications > CPRI > Altera CPRI IP

from Altera Corporation

OpenCore Plus Support

The Common Public Radio Interface (CPRI) is an initiative to define a publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. CPRI allows the use of a distributed architecture where basestations, containing the REC, are connected to remote radio heads via lossless fibre links that carry the CPRI data. This architecture reduces costs for service providers because only the remote radio heads containing the RE need to be situated in environmentally challenging locations. The basestations can be centrally located in less challenging locations where footprint, climate, and availability of power are more easily managed.

Altera now offers a complete easy-to-use intellectual property (IP) core for building CPRI v4.1 and lower interfaces to speed development time and allow you to focus on product differentiation.

Features

  • Highly configurable
    • REC and RE mode configuration support
    • Programmable line rates up to 6.144 Gbps as introduced in CPRI specification v4.1; clock rates as low as 153.6 MHz for 6.144-Gbps operation to ease timing closure 
    • Support for basic and advanced IQ data mapping modes
    • Up to 24 antenna carriers per IP core
    • 16-bit and lower sampling widths
    • Integrated 10/100 Ethernet MAC and HDLC controllers for control and management layers
    • Support for multi-mode air interface configurations
    • Auxiliary port can be used to enable multi-hop system topologies
    • Source code license available for additional fee 
  • Easy to use
    • MegaWizardTM Plug-In Manager interface to configure IP parameters
    • Accurate delay measurement and calibration 
    • Support for Altera’s standard Avalon® memory mapped (MM) and Avalon streaming (ST) interfaces allow you to simplify system-level design integration through the use of Altera's SOPC Builder tool
    • Included test bench guides you through the operation of typical system configuration and provides example code for common CPRI start-up sequences

Figure 1 shows a high-level block diagram for Altera's CPRI IP solution.

Figure 1. Altera CPRI IP Core Block Diagram

Figure 1. Altera CPRI IP Core Block Diagram

Altera's CPRI IP core is supported on the following device families:

  • Stratix® IV FPGAs
  • Arria® II GX FPGAs
  • HardCopy® IV ASICs
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