Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

IP Products    Embedded Processors    Interfaces & Peripherals    DSP    Communications           Cell/Packet           SONET/SDH           PDH (T/E Carrier)           Encoding/Decoding           HDLC           UTOPIA           POS-PHY           Bluetooth           FlexBus           CSIX           Additional Functions           Consortiums           Literature     About IP       Designing with IP       Evaluate and Download IP       IP Certifications       System Design       Request IP     IP Industry Partners       About AMPP Program       AMPP Core Partners

Home > Products > Intellectual Property > Communications > SONET/SDH > STM-0/1/4 (STS-1/3/12) Deframer Print This Page Subscribe to Email STM-0/1/4 (STS-1/3/12) Deframer from Aliathon Features Supports all SONET equivalents of SDH functionality Detects SDH frames for STM-0/1/4 May be dynamically switched between rates Generates LOS, OOF, and LOF alarms Descrambles the SDH frames Extracts regenerator section overhead and detects B1 errors Extracts multiplex section overhead and detects B2 errors Processes all AU pointers (up to 12 for VC3 over STM4) Extracts VC3, VC4, and VC4-4c, channelized and single-channel All combinations of VCs are supported VC settings may be dynamically reconfigured on a per VC basis Detects B3 errors for all VCs Extracts higher order path overhead Block Diagram Figure 1 shows a block diagram of the function. Figure 1. Block Diagram Click for full detail (49KB) Description The Aliathon STM-0/1/4 (STS-1/3/12) Deframer core provides a flexible, resource-efficient, programmable logic based solution for SONET/SDH interfaces. It supports both concatenated payloads (e.g., VC4-4c over STM-4) and channelized (e.g., multiple VC3s over STM-1). The core supports all of the specified rates and may be dynamically switched to any of those rates. The core is supported for Stratix® II, Stratix GX, and Cyclone™ FPGAs. Device Utilization & Performance Table 1 lists the typical device utilization for the megafunction. Table 1. Typical Device Utilization for the Megafunction Target Device Speed Grade Utilization Performance (fMAX) Parameter Setting LEs (1) ESBs (2) Cyclone -7 1,271 - 100+ MHz Contact Aliathon Stratix -7 1,268 - 100+ MHz Contact Aliathon Stratix II -5 631 - 100+ MHz Contact Aliathon Notes: LEs = Logic elements. The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software. ESBs = Embedded system blocks Contact Information For additional information, contact Aliathon at: Evans Business Centre Pitreavie Court Dunfermline Fife KY11 8UU United Kingdom Tel: +44 (0) 1383 737736 Fax: +44 (0) 1383 749501 E-mail: info@aliathon.com URL: www.aliathon.com Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation