STM-0/1/4 (STS-1/3/12) Demapper

from Aliathon

Features

• Accepts up to 12 input VCs
  • VCs can be a mix of VC3, VC4, and VC4-4c
• Demaps TUG3 from VC4 and TUG2 from VC3 or TUG3 
• Demaps TUs (TU11, TU12, and TU2) from TUG2
  • TU type can be dynamically configured on a per TUG2 basis
  • TU3 within TUG3 is also supported, as is VC11 over TU12
• Processes all TU pointers
  • Including the TU3 pointer for TU3 over TUG3
• Extracts all lower-order path overhead
• Verifies BIP-2 calculations (B3 in the case of TU3 over TUG3). VC settings may be dynamically reconfigured on a per VC basis
• Demaps PDH from VC and TU payloads
  • All mappings for TU11, TU12, TU2, VC3, and VC4 are supported
  • Demapping type may be dynamically configured on a per-TU/VC basis
• Provides a multi-channel output of up to 336 TUs (TU11 over STM-4)
• Plugs directly into SDH deframer core for a complete SDH solution
  • Also plugs into PDH deframer cores (E1/T1 and E3/T3)

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. Block Diagram

Click for full detail (49 KB)

Description

Aliathon STM-0/1/4 (STS-1/3/12) Demapper core provides a flexible, resource-efficient, programmable logic based solution for SONET/SDH interfaces. The core supports all mappings (e.g., 336 TU11's in STM-4, 3 TU3's in STM-1, or any combination) and may be dynamically switched between any of the mappings. The core is supported for Stratix^® II, Stratix GX, and Cyclone™ FPGAs.

Device Utilization & Performance

Table 1 lists the typical device utilization for the megafunction.

Notes:

1. LEs = Logic elements. The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus^® II software.
2. ESBs = Embedded system blocks

Contact Information

For additional information, contact Aliathon at:

Evans Business Centre
Pitreavie Court
Dunfermline
Fife KY11 8UU
United Kingdom

Tel: +44 (0) 1383 737736
Fax: +44 (0) 1383 749501

E-mail: info@aliathon.com
URL: www.aliathon.com