Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
   DSP
   Communications
          Cell/Packet
          SONET/SDH
          PDH (T/E Carrier)
          Encoding/Decoding
          HDLC
          UTOPIA
          POS-PHY
          Bluetooth
          FlexBus
          CSIX
          Additional Functions
          Consortiums
          Literature
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

STM-0/1/4 (STS-1/3/12) Mapper

from Aliathon

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • Generates up to 12 VC payloads
    • VCs can be a mix of VC3 and VC4
  • Maps TUG3 into VC4 and TUG3 into VC3 or TUG3
  • Maps TUs (TU11, TU12, and TU2) into TUG2
    • TU type can be dynamically configured on a per TUG2 basis
    • TU3 within TUG3 is also supported, as is VC11 over TU12
  • Generates all TU pointers
    • Including the TU3 pointer for TU3 over TUG3
  • Inserts all lower-order path overhead
  • Calculates BIP-2 (B3 in the case of TU3 over TUG3)
  • Maps PDH signals into VC and TU payloads
    • All mappings for TU11, TU12, TU2, VC3, and VC4 are supported
    • Mapping type may be dynamically configured on a per-TU/VC basis
  • Accepts a multi-channel input of up to 336 TU payloads (TU11 over STM-4)
  • Plugs directly into SDH Framer core for a complete SDH solution
    • Also plugs into PDH Framer cores (E1/T1 and E3/T3)

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. Mapper Block Diagram
Figure 1. Demaper Block DiagramClick for full detail (58 KB)

Description

The Aliathon STM-0/1/4 (STS-1/3/12) Mapper core provides a flexible, resource-efficient, programmable logic based solution for SONET/SDH interfaces. The core supports all mappings (e.g., 336 TU11's in STM-4, 3 TU3's in STM-1, or any combination) and may be dynamically switched between any of the mappings. The core is supported for Stratix® II, Stratix GX, and Cyclone™ FPGAs.

Device Utilization & Performance

Table 1 lists the typical device utilization for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device Speed Grade Utilization Performance
(fMAX)
Parameter
Setting
LEs (1) ESBs (2)
Cyclone -7 2140 - 90+ MHz Contact Aliathon
Stratix -7 1952 - 90+ MHz Contact Aliathon
Stratix II -5 1114 - 100+ MHz Contact Aliathon

Notes:

  1. LEs = Logic elements. The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
  2. ESBs = Embedded system blocks

Contact Information

For additional information, contact Aliathon at:

Evans Business Centre
Pitreavie Court
Dunfermline
Fife KY11 8UU
United Kingdom

Tel: +44 (0) 1383 737736
Fax: +44 (0) 1383 749501

E-mail: info@aliathon.com
URL: www.aliathon.com

  Please Give Us Feedback