SPI-4.2 Foundation & Manager
Features
SPI-4.2 foundation features:
- Object interchange format (OIF)-compliant SPI-4 Phase 2 (compatible with Saturn Group POS-PHY L4)
- Fully synchronous design, which exceeds 800 Mbps (400-MHz DDR)
- PluriBus 64- or 128-bit user interface for easy integration with user's application or seamless integration with other Modelware cores for bridge and multiplexer/demultiplexer designs
- Out-of-band packet signaling with start of packet (SOP), end of packet (EOP), mod, and err on PluriBus user interface
- SOP data to most significant bit (MSB) alignment function
- Handles continuous back-to-back EOP (2N + 1-byte packets) with shared control words
- Low-speed (LVTTL) and high-speed (LVDS) FIFO buffer status interfaces
- Hitless bandwidth provisioning
- Dual in-line package (DIP)-4 parity generation/checking
- Training sequence generation and detection
- Normal and high-speed FIFO buffer status channel
SPI-4.2 manager features (in addition to foundation features):
- Multi-channel FIFO buffers with programmable size per channel
- Automatic sink flow control generation (RStat)
- Source flow control processing (TStat), credit management per channel, and source data scheduler
- Automatic handling of Maxburst1 and Maxburst2 per channel
- Packet segmentation and reassembly (store-and-forward)
- SOP/EOP checking
Additional advanced features:
- Supports dynamic alignment in Stratix® GX devices
- Transmission data packer that reduces or eliminates idle words between packets
- User interface with programmable pauses that allow post-burst or post-EOP processing
- Several programmable features that take into account different interpretations of the SPI-4.2 specification.
- ASIC support
Block Diagram
Figure 1 shows a block diagram of the SPI-4.2 foundation sink, and Figure 2 shows a block diagram of the SPI-4.2 foundation source.
Figure 1. Foundation Sink Block Diagram
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Figure 2. Foundation Source Block Diagram
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Description
SPI-4.2 Foundation
The foundation core interfaces to the Altera® atllvds_rx and altlvds_tx blocks that perform the electrical termination and convert between the 16-bit data + 1 control bit DDR bus and 64-bit data + 4 control bits at half of the interface clock frequency. If the high-speed status option is implemented, the atllvds_rx and altlvds_tx blocks are also used for data rate conversion circuitry between the 2-bit DDR status on the SPI-4.2 interface and 8-bit single data rate on the core logic side.
On the user's side, the SPI-4.2 core interfaces to a single- or multi-channel application through a single FIFO buffer subsystem in each direction. The SPI-4.2 sink section stores data received for a particular port in a FIFO buffer with the port address information, decoded from the control word preceding the data burst. The SPI-4.2 source section reads the port number and packet data from the source FIFO buffer and transmits on the SPI-4.2 interface.
The core also passes the decoded per-channel user FIFO buffer status between the SPI-4.2 interface and the user's application in both directions. The SPI-4.2 sink section transmits the FIFO buffer status information provided by the user's circuitry. The SPI-4.2 source section receives the far-end FIFO buffer status from the FIFO buffer status channel and makes it available for reading by the user's application.
SPI-4.2 Manager
On the user's side, the SPI-4.2 manager core interfaces to multiple channels through multi-channel FIFO buffers. The core handles the FIFO buffer status channel completely with no user interaction. The SPI-4.2 sink section transmits the FIFO buffer status information for each channel according to the fill level of the sink multi-channel FIFO buffers. It then stores the data received for that particular channel into that channel's FIFO buffer. The SPI-4.2 source section receives the peer device's FIFO buffer status from the FIFO buffer status channel and uses the flow control information in the credit manager for scheduling data transfers. The source section transmits data to a particular channel from that channel's FIFO buffer.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| LEs (1) |
ESBs (2) |
| EP1S40 |
8,670 |
18 M4Ks |
400 MHz |
16-Channel Foundation
Dynamic BW Reprovisioning |
| EP1S40 |
12,130 |
30 M4Ks |
400 MHz |
16-Channel Foundation
High-speed Status Channel |
| EP1S40 |
19,160 |
100 M4Ks |
400 MHz |
8-Channel Manager
Dynamic BW Reprovisioning |
Notes:
- LE = logic element
- ESB = embedded systems block
Deliverables
- Core (RTL or netlist)
- Test bench
- Simulation scripts
- Synthesis scripts
- Quartus® II design software files
- Documentation
Contact Information
For additional information, contact Modelware:
Modelware (USA)
10 West Bergen Place
Suite 105
Red Bank, NJ 07701
Tel. (732) 936-1808
Fax (732) 936-1839
E-mail: altera@modelware.com
URL: www.modelware.com
Modelware (Europe)
Kuechel str. 14
96047 Bamberg, Germany
Tel: +49 951 299-9870
Fax: +49 951 299-9872
Email: altera@modelware.com
URL: www.modelware.com
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