To help shorten your design time, Altera provides full production licenses for some of its most popular intellectual property (IP) cores (shown in Table 1) in the Altera® IP Base Suite, which is free with a Quartus® II subscription.
If you are a subscriber of Quartus II Subscription Edition software, simply download your license file to take advantage of the IP Base Suite:
- Download Quartus II Subscription Edition software package. The entire MegaCore® IP library, including the IP Base Suite, is combined with Quartus II download and installation.
- Update your license file at www.altera.com/licensing.
If you do not have an active subscription to Quartus II software, you can still install and start designing with any Altera IP core via our unique OpenCore Plus (PDF) simulation and hardware evaluation feature.
If you are not a subscriber and would like to be, please contact your local Altera Sales representative.
Questions? Please see IP Base Suite Questions and Answers.
| Table 1. MegaCore Functions in the IP Base Suite | |
| IP MegaCore Functions | Description |
|---|---|
| FIR Compiler | Over 12 major finite impulse response (FIR) filter architectures for use across all digital signal processing (DSP) applications. Supports maximum clock frequency of over 400-MHz performance in Stratix® series FPGAs. |
| FIR Compiler II | Provides significantly lower FPGA resource usage and increased performance than the original FIR Compiler for most FIR filter implementations. FIR filter performance, internal pipelining, and logic resource usage are optimized based upon user inputs. |
| NCO Compiler | Optimized for digital phase-locked loop (PLL) and digital interface functions. Supports multiple ROM-, CORDIC-, and multiplier-based architectures. |
| FFT Compiler | A high-performance, highly parameterizable fast Fourier transform (FFT) processor. The FFT function implements a Radix-2/4 decimation-in-frequency FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation. |
| High Performance Memory Controller II | High-performance DDR1, DDR2, and DDR3 SDRAM memory interface controllers with integrated SOPC Builder support. Supports up to 1,066-Mbps DDR3 memory interfaces in Stratix III and Stratix IV FPGAs. |
| DDR SDRAM Controller | Flexible DDR SDRAM memory interface controller with integrated SOPC Builder support. Includes complete system timing analysis and automatic constraints setting. |
| DDR SDRAM High-Performance Controller | Flexible, high-performance DDR SDRAM memory interface controller. Includes complete system timing analysis and automatic constraints setting. Integrated SOPC Builder support. |
| DDR2 SDRAM Controller | Flexible DDR2 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 533-Mbps DDR2 memory interfaces in Stratix II FPGAs. |
| DDR2 SDRAM High-Performance Controller | Flexible, high-performance DDR2 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 800-Mbps DDR2 memory interfaces in Stratix III FPGAs. |
| DDR3 SDRAM High-Performance Controller | Flexible, high-performance DDR3 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 400-Mbps DDR3 memory interfaces in Stratix III FPGAs. |
| QDR II SRAM Controller | QDR II SRAM memory interface controller supports burst-of-2 and burst-of-4 QDRII devices. |
| QDR II/QDR II+ SRAM Controller with UniPHY | QDR II/QDR II+ SRAM memory interface controller supports burst-of-2 and burst-of-4 QDRII devices at speeds up to 400 MHz in Stratix IV FPGAs. The controller also utilizes the low-latency UniPHY interface. |
| RLDRAM II Controller | RLDRAM II memory interface controller supports common I/O and separate I/O RLDRAM II devices. Supports up to 300-MHz RLDRAM II memory interfaces in Stratix II FPGAs. |
| RLDRAM II Controller with UniPHY | RLDRAM II memory interface controller supports common I/O and separate I/O RLDRAM II devices. Supports up to 400-MHz RLDRAM II memory interfaces in Stratix IV FPGAs. The controller also utilizes the low-latency UniPHY interface. |
| SerialLite II | SerialLite II is Altera's second-generation lightweight serial interconnect protocol supporting a wide array of chip-to-chip, board-to-board, and backplane applications. SerialLite II builds on the success of SerialLite, extending the performance range from 622 Mbps to 102 Gbps in Stratix II GX FPGAs, and reducing the logic requirements by an average of 60 percent to deliver the lowest cost serial interconnect solution. |
