Free IP Base Suite Licenses With Active Quartus II Subscription
To help shorten your design time, Altera provides some of its most popular intellectual property (IP) cores (shown in Table 1) with the Altera® IP Base Suite, which is completely free with a Quartus® II subscription.
If you are a subscriber to one of these Quartus II products, simply download a new license file to take advantage of the IP Base Suite:
- Download Quartus II Subscription Edition software package and install the MegaCore® IP library. New subscribers can install the MegaCore library from the Quartus II DVD.
- Update your license file at www.altera.com/licensing.
If you do not have an active subscription to the Quartus II software, you may still install and start designing with any Altera IP core via our unique OpenCore Plus (PDF) simulation and hardware evaluation feature.
If you are not a subscriber and would like to be, please contact your local Altera Sales representative.
Questions? Please see IP Base Suite Questions and Answers.
| Table 1. MegaCore Functions in the IP Base Suite |
| IP MegaCore Functions |
Description |
| FIR Compiler |
Over 12 major finite impulse response (FIR) filter architectures for use across all digital signal processing (DSP) applications. Supports maximum clock frequency of over 400-MHz performance in Stratix® series FPGAs. |
| NCO Compiler |
Optimized for digital phase-locked loop (PLL) and digital interface functions. Supports multiple ROM-, CORDIC-, and multiplier-based architectures. |
| FFT Compiler |
A high-performance, highly parameterizable fast Fourier transform (FFT) processor. The FFT function implements a Radix-2/4 decimation-in-frequency FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation. |
| DDR SDRAM Controller |
Flexible DDR SDRAM memory interface controller with integrated system-on-a-programmable-chip (SOPC) Builder support. Includes complete system timing analysis and automatic constraints setting. |
| DDR SDRAM High-Performance Controller |
Flexible, high-performance DDR SDRAM memory interface controller. Includes complete system timing analysis and automatic constraints setting. Integrated SOPC Builder support. |
| DDR2 SDRAM Controller |
Flexible DDR2 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 533-Mbps DDR2 memory interfaces in Stratix II FPGAs. |
| DDR2 SDRAM High-Performance Controller |
Flexible, high-performance DDR2 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 800-Mbps DDR2 memory interfaces in Stratix III FPGAs. |
| DDR3 SDRAM High-Performance Controller |
Flexible, high performance DDR3 SDRAM memory interface controller with integrated SOPC Builder support. Supports up to 400-Mbps DDR3 memory interfaces in Stratix III FPGAs. |
| QDRII SRAM Controller |
QDRII SRAM memory interface controller supports burst-of-2 and burst-of-4 QDRII devices. |
| RLDRAM II Controller |
RLDRAM II memory interface controller supports common I/O and separate I/O RLDRAM II devices. Supports up to 300-MHz RLDRAM II memory interfaces in Stratix II FPGAs. |
| SerialLite II |
SerialLite II is Altera’s second-generation lightweight serial interconnect protocol supporting a wide array of chip-to-chip, board-to-board, and backplane applications. SerialLite II builds on the success of SerialLite, extending the performance range from 622 Mbps to 102 Gbps in Stratix II GX FPGAs, and reducing the logic requirements by an average of 60 percent to deliver the lowest-cost serial interconnect solution. |
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