Altera and its third-party intellectual property (IP) partners offer a large selection of off-the-shelf IP cores optimized for Altera® devices. All Altera IP cores are rigorously tested and optimized for the highest performance and lowest cost in Altera's programmable logic devices (PLDs). You can implement these parameterized blocks of IP easily, reducing design and test time.
Time to Market
Use of IP cores reduces time to market because you can avoid the process of designing standardized functions from scratch. Altera and partner IP enable you to concentrate on product improvement and differentiation.
Altera’s OpenCore Plus evaluation feature allows you to simulate the behavior of an Altera IP core within the targeted system, verify the functionality of the design, and evaluate its size and speed quickly and easily. In addition, the Quartus® II development software generates time-limited programming files for designs containing Altera IP, allowing device programming and design verification before license purchase. Many Partner IP cores also support this evaluation flow.
For more information about core download, evaluation, and licensing, visit Altera's Getting Started page.
Altera IP cores are fully parameterizable. The IP configuration GUI shown in Figure 1 allows you to quickly and easily view documentation, specify parameters, set up third-party tools, and generate all the files necessary for integrating the parameterized Altera IP core into a design. You can launch an IP configuration GUI from the Quartus II software’s MegaWizard® Plug-In Manager, from the Qsys or SOPC Builder tools, or the DSP Builder tool.
Figure 1. PCI Express® Configuration Panel
You can generate IP functional simulation models for any parameterized Altera IP variant. An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model file produced by the Quartus II software. The models allow for fast functional simulation of IP using industry-standard VHDL or Verilog HDL simulators.
For post place-and-route simulation, the Quartus II software provides a flexible simulation environment through a native simulator within the Quartus II software or through VHDL and Verilog output netlists.
Synthesis and Compilation
To ensure consistent performance and facilitate drop-in instantiation of cores, optimized HDL code ready for compilation through the Quartus II development software is generated.
Altera and its partners offer a wide variety of development kits that are the ideal platforms to develop and test designs containing IP cores. Altera’s IP core hardware evaluation and development kit portfolio make a powerful combination that translates into the fastest possible time to market. The development kit page contains a complete list of Altera and partner development kits.