C32025 Digital Signal Processor

from CAST, Inc.

Features

• Control unit
  • 16-bit instruction decoding
  • Repeat instructions for efficient use of program space and enhanced execution
• Central arithmetic logic unit (ALU)
  • 16-bit parallel shifter; 32-bit arithmetic and logical operations
  • 16- by 16-bit parallel multiplier with a 32-bit product
  • 32-bit accumulator with output shifter
  • Single-cycle multiply-and-accumulate instructions
• Auxiliary registers
  • Eight 16-bit registers for indirect addressing or temporary data storage
  • 16-bit auxiliary register arithmetic unit including operations with reversed-carry propagation
• Memory addressing modes
  • Direct mode uses a 9-bit page pointer and instruction word's lowest 7-bits
  • Indirect mode uses the auxiliary register file
  • Immediate mode is less than 16-bit via the instruction word, or full 16-bit long immediate following the instruction word
  • Block moves for data/program management
• Eight-level hardware stack
• Interrupt controller with six interrupt sources, excluding reset and a software interrupt
• Synchronous serial port for direct codec interface
• 16-bit reload timer
• Program memory organization
  • 4 K words of internal ROM
  • Internal 256-word RAM block configurable either as program or data space
  • 64 K words of external program space
• Data memory organization
  • Two internal 256-word blocks and one 32-word RAM block
  • 64 K words of external data space
  • Six memory-mapped registers
• 16 input and 16 output channels
• Wait states for interfacing slower off-chip devices
• Multiprocessing support
  • Global data memory interface
  • Synchronization input for synchronous multiprocessor configurations
  • Concurrent DMA using an extended hold operation

Block Diagram

Description

The C32025 megafunction is a 16-bit, fixed-point digital signal processor. It combines the flexibility of a high-speed controller with the numerical capability of an array processor. The C32025 has the same instruction set as the TMS320C25 and also provides the same interrupts, serial interface, and timer.

The C32025 is a microcode-free design developed for reuse in application-specific integrated circuit (ASIC) and programmable logic device (PLD) implementations. The design is strictly synchronous with positive-edge clocking and synchronous reset, and no internal tri-states.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Notes:

1. The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus^® II software.
2. Implemented with 544- by 16-bit RAM and 1048- by 16-bit ROM
3. Implemented with 544- by 16-bit RAM and 4096- by 16-bit ROM  

Deliverables

• Encrypted licenses
  • Post-synthesis EDIF or Altera hardware description language (AHDL)
  • Assignment and configuration
  • Symbol file
  • Include file
  • Sample design CHIP_C32025
  • Vectors for testing the functionality of the megafunction
• HDL source licenses
  • HDL register transfer level (RTL) source code
  • Simulation script
  • Synthesis script
  • Sample CHIP_C32025 design (TMS320C25-compatible design)
  • Testbench
  • Collection of tests executed directly by the testbench

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: info@cast-inc.com
URL: www.cast-inc.com