Altera Floating Point Megafunctions
from Altera Corporation
Introduction
Many modern digital signal processing (DSP) systems employ floating-point functionality to achieve the high degree of numeric precision and dynamic range that most applications require. Applications such as radar, sonar, bio and molecular science, financial modeling, advanced wireless antenna processing, medical imaging, image analytics and synthesis, and precision control are just a few applications that are creating a demand for floating-point capabilities in FPGAs. Furthermore, as FPGAs continue to grow in size and capability, they are becoming the highest performance platform available for any type of floating-point-based algorithm or computation.
Altera provides IEEE 754-compliant floating-point megafunctions that can be used in any Altera® device family. These megafunctions include:
- Addition/subtraction [altfp_add_sub]
- Multiplication [altfp_mult]
- Division [altfp_div]
- Square root [altfp_sqrt]
- Compare [altfp_compare]
Features
Floating-point computation performance is typically a balanced combination of the frequency at which the operators run and the pipeline latency of the operator hardware; this product yields a measure of GFlop performance metric. When designing for maximum GFlop performance in an FPGA, the total number of operators that can be placed in an FPGA is vital. As such, the Altera floating-point megafunctions can be parameterized in many different ways to fine-tune GFlop performance (or similarly for other key metrics such as power and area) to meet the application-specific requirements. The configurable features include:
- Single and double precision selection
- Single extended configurable precision
- Operator latency versus area tradeoff
- Reduced functionality
- Optional de-normalized number support
- Reduced rounding accuracy
- Optional indefinite support
- Support for dedicated multiplier circuitry (multiplier only)
- Optional add or subtract-only mode (adder/subtractor only)
Typical Performance
Table 1 lists the typical performance for each floating-point operator. All results are quoted based on the Stratix® III device family.
| Table 1. Typical Floating-Point Operator Performance |
| Floating Point Operator |
Latency
Clock Cycles |
fMAX
(MHz) |
Area |
| Logic Elements (LEs) |
DSP (1) |
| Adder/Subtractor |
| Single |
14 |
474 |
1,086 |
0 |
| Double |
14 |
419 |
2,078 |
0 |
| Multiplier |
| Single |
11 |
458 |
495 |
4 |
| Double |
11 |
405 |
903 |
10 |
| Divider |
| Single |
33 |
385 |
4,712 |
0 |
| Double |
61 |
279 |
19,277 |
0 |
| Square root |
| Single |
28 |
392 |
1,212 |
0 |
| Double |
57 |
311 |
4,713 |
0 |
| Compare |
| Single |
3 |
888 |
76 |
0 |
| Double |
3 |
739 |
135 |
0 |
Note:
- DSP in Stratix III devices is an 18-bit block.
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