Floating-Point Operator Library
Features
- Programmable register length and initial value
- Automatic resizing and feedback selection (2 to 32 bits)
- Feedback architecture designed for maximum speed
- Multiple user-selectable configurations
Block Diagram
Figure 1 shows the block diagram for the floating point operator megafunction.
Description
Floating-point operation implementation in programmable logic is now easy with the Amphion floating-point operator library, which consists of the following:
- Floating-point adder—Registrable output and optional pipeline cuts, both addends have the same exponent size.
- Floating-point divider—Using radix-2 SR 0 array. Default quotient value when in operation = 0/0.
- Floating-point multiplier
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance (fMAX) |
Parameter Setting |
| Logic Cells |
EABs(1) |
| EPF10K30A |
-1 |
618 |
0 |
35 MHz |
Floating-point adder
(M=16, E=6, P=3) |
| 785 |
0 |
37 MHz |
Floating-point multiplier
(M=16, E=6, P=2) |
| 2,051 |
0 |
41 MHz |
Floating-point divider
(M=16, E=6, P=6) |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Amphion Semiconductor, Ltd. at:
Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001
Email: info@amphion.com
URL: http://www.amphion.com
|
Literature
> 
