DFPDIV Floating-Point Pipelined Divider Unit
Features
- Fully complies with IEEE-754 specification
- Single-precision real-format support
- Simple interface
- No programming required
- Fifteen levels of pipelining
- Fully accurate and precise
- Results available at every clock
- Overflow, underflow, and invalid operation flags
- Fully configurable
- Fully synthesizable, static-synchronous design with no internal tri-states
Description
The DFPDIV megafunction uses the pipelined mathematics algorithm to divide two arguments. The input number format complies with the IEEE 754 specification, and the function supports single-precision real numbers. The divide operation is pipelined to 15 levels, and the input data is fed in at every clock cycle. The first result appears after 15 clock periods of latency, and the subsequent results are available at each clock cycle.
Block Diagram
Figure 1 shows the block diagram for the DFPDIV megafunction.
Figure 1. Block Diagram for the DFPDIV Megafunction
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Parameter Setting |
| Logic Cells |
Performance
(fMAX) |
| FLEX® EP10K100E |
-1 |
3338 |
31 MHz |
Contact Digital Core Design |
| APEXTM EP20K100E |
-1 |
3428 |
31 MHz |
Contact Digital Core Design |
| ACEX® EP1K100 |
-1 |
3338 |
34 MHz |
Contact Digital Core Design |
Contact Information
For additional information, contact Digital Core Design at:
Digital Core Design
Wroclawska 94
41-902 Bytom, Poland
Tel. +48 32 282 82 66
Fax +48 32 282 74 37
E-mail: info@dcd.com.pl
URL: www.dcd.com.pl
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