SHA-1
Features
- Suitable for data authentication applications
- Fully synchronous design
- Available in VHDL or Verilog
Description
This megafunction is a fully compliant implementation of the secure hash algorithm (SHA-1). It computes a 160-bit message digest for messages up to (216- 1) bits.
Developed for easy reuse in ASIC and FPGA applications, the SHA-1 is available optimized for several technologies with competitive utilization and performance characteristics.
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1: Block Diagram 
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
(fmax) |
| LEs |
EABs |
I/O Pins |
| EPF1K50 |
-1 |
1,846 |
- |
200 |
54 MHz |
| EP20K100E |
-1 |
1,916 |
- |
200 |
50 MHz |
| EP1S10 |
-5 |
1,585 |
- |
200 |
97 MHz |
| EP1C12 |
-6 |
1,682 |
- |
200 |
86 MHz |
Notes:
- LEs = Logic elements
- EABs = Embedded array blocks
Deliverables
- EDIF netlist
- Assignment & configuration
- Symbol file
- Include file
- Vectors for testing the functionality of the megafunction including expected results
- Documentation
Contact Information
For additional information, contact CAST. Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
URL: www.cast-inc.com
|
Literature
> 
