High-Speed AES Encryption Cores (RJDCEO/RJDCDO/RJDCED)
Features
- >2.5 Gbits per second (Gbps) throughput for fiber-speed encryption
- Key-agility on both encryption and decryption allows keys to be switched without stalling the core
- Simple streaming architecture obviates the need for elaborate control logic outside the core
- Bypass control allows data flow-through for selective encryption
- Simple 32-bit data and key ports reduce logic required to interface to high-speed standards
Block Diagram
Figure 1 shows a block diagram of the AES encryption core.
Figure 1: AES Encryption Cores (RJDCEO/RJDCDO/RJDCED)
Overview
D'Crypt's AES core is a high-performance pipelined implementation of the AES (Rijndael) encryption algorithm. Optimized for programmable logic device (PLD) architectures, the function achieves in excess of 2.5-Gbps encryption and decryption throughput on 128-bit block sizes when implemented on an Altera® APEX™ 20KE or equivalent device. It employs a 128-bit key and features zero key-setup latency on both encryption and decryption. With key-agility and selective bypass control, D'Crypt's AES core is the ideal building block for high-performance packet-smart routers and switches.
Device Utilization Example
Table 1 lists the typical device utilization results for the high-speed AES encryption and decryption megafunctions.
| Table 1. Typical Device Utilization |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs/ESBs (1) |
| APEX EP20K400E |
-1 |
6167 |
50 |
120.39 MHz |
Encryption Core
Contact D'Crypt |
| APEX EP20K400E |
-1 |
6784 |
50 |
118.47 MHz |
Encryption Core
Contact D'Crypt | Note:
- EAB = embedded array block; ESB = embedded system block < /li >
Contact Information
For additional information, contact D'Crypt at:
D'Crypt Pte Ltd.
20 Ayer Rajah Crescent
#08- 08 Technopreneur Centre
Singapore 139964
Phone: +65 773 9016
Fax: +65 873 0796
E-mail: ipcore@d-crypt.com
WWW: http://www.d-crypt.com
|
Literature
> 
