DVB FEC Codec
Features
- Complete digital video broadcast (DVB) forward error correction (FEC) solution, which includes:
- Scrambler/descrambler
- Reed-Solomon encoder/decoder
- Interleaver/deinterleaver
- 8-bit parallel data symbol input and output
- Bit-rate and symbol-rate clock required
- Reed-Solomon code generator polynomial according to ETS 300-429
- Reed-Solomon field generator polynomial according to ETS 300-429
- Reed-Solomon codeword format (204,188)
- Two input control signals provided to both transmit (Tx) and receive (Rx)
- Low to high transition at the start of the codeword and high to low transition at the end of the codeword
- Low to high transition at the start of the codeword and high to low transition at the start of the parity
- Rx function also has input for external synchronizing signal for descrambler block
- Statistics reporting
- Interleave depth = 12
- Constant latency regardless of mode of operation, except when external random access memory (RAM) removed
- Encoder and decoder supplied as separate functions
Block Diagram
Figure 1 shows the block diagram for the DVB FEC Codec megafunction.
| Figure 1. DVB FEC Codec Block Diagram |
 |
View Full Size
Description
Each block in the transmit function has a fixed latency, and when disabled will pass the data unmodified with the same latency.
The scrambler block is known as the multiplex adaptation and energy dispersal block in the ETS DVB specification. This block contains pseudo-random binary sequence (PRBS) generators to ensure an even 1-to-0 ratio in the transmitted data stream. To ensure that transmitter and receiver synchronize their PRBS generators, the first byte in every eight packets is inverted. In the normal MPEG-2 scheme, this byte will be a 47 hex value.
The scrambler block waits for the first byte of the first packet immediately after reset is de-asserted, by monitoring the state of the TxIPIn and TxDVIn signals. The first byte after reset for which these signals are asserted is assumed to be the synchronous byte, and is inverted. Thereafter the first byte in every eighth packet is also inverted.
The Reed-Solomon encoder block generates parity symbols and inserts these in the data stream when RxDVIn is asserted and RxIPIn is de-asserted. The value of the input data (RxDIn) at this time is ignored.
The convolutional interleaver has an interleave depth of 12 and requires the use of an external DPRAM to perform this function. It passes bytes through the block with varying latency. The sync bytes always pass with minimum latency. The total transmit function latency for invalid bytes, sync bytes, and every 12th byte—or for all bytes when the interleaver is disabled—is 4 ticks.
Each block in the receiver function has a fixed latency, and when disabled will pass the data unmodified with the same latency.
The convolutional deinterleaver assumes that the first valid byte after reset (first byte with RxDVIn asserted) is a sync byte and delays this byte by the maximum fixed delay (11 packets). Thereafter, every twelfth byte will have the same delay. Bytes are delayed by successively smaller amounts until the eleventh byte, which has zero delay applied. Invalid bytes are not delayed, and when the deinterleaver is disabled, all bytes are passed though with no delay.
The Reed-Solomon decoder holds a packet until it has been either completely corrected, or the number of errors is too great. In the latter case the packet is passed out with the RxUncOut signal asserted for the entire packet. This makes it easier for downstream hardware to discard uncorrectable packets. The decoder also maintains a count of the number of corrected bytes in the 0-to-8 range. This value is held after the end of a packet until the first byte of the next packet, when it is cleared (or set to 1 if the first byte was corrected). The function asserts RxCorOut and updates the count at the same time as it outputs each corrected byte.
The descrambler block needs knowledge of which synchronous byte is the eighth packet to reset its PRBS. Since the data stream in this application may not be MPEG-2 compliant, the Rx function must be told by external hardware when this synchronous byte arrives. The RxFirstPkt signal should be asserted when the synchronous byte is driven on the RxDIn pins. This signal is delayed appropriately to match the delay through the convolutional deinterleaver and the Reed-Solomon decoder. There is no synchronization mechanism for a PRBS generator for non-valid bytes; therefore, only bytes with RxDVOut asserted will be correct.
The total delay through the Rx function is 610 clock ticks for invalid bytes and for bytes which are 11 bytes after the synchronous byte, and every twelfth byte thereafter, or all bytes when the deinterleaver is disabled. The combination of the Tx function interleaver and Rx function deinterleaver delays results in an additional overall delay of 11 packets when interleaving is enabled.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| EPF10K50RC240 |
-3 |
1,915 |
6 |
44.376 MHz |
Maximum symbol rate 5.547 MHz
|
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Amphion Semiconductor, Ltd. at:
Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001
Email: info@amphion.com
URL: http://www.amphion.com
|
Literature
> 
