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Overview
The TurboConcept TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for 3GPP/LTE specifications. It offers several algorithm options to meet various trade-offs between error correction performance and core complexity.
The decoder architecture is high-throughput oriented for all block sizes. Four throughput profiles are available through this parallel decoding architecture:
- Single processor core: 25 Mbps
- Dual processor core: 45 Mbps
- Four processor core: 85 Mbps
- Eight processor core: 160 Mbps
Throughput depends on the selected programmable logic device (PLD) and varies with block size and number of decoding iterations. Please contact TurboConcept for additional information.
An efficient early iteration stopping feature can be enabled to significantly increase the average throughput and reduce power consumption.
A corresponding 2GPP/LTE CTC encoder core is also available. Please contact TurboConcept for more details.
Features
- Compliant with 3GPP-LTE
- Block sizes covered from 40 to 6144 payload bits, switchable on-the-fly
- Native code rate 1/3 - other code rates supported through external rate matching
- Near floating-point error correction performance
- High throughput Max-Log-MAP algorithm
- Efficient and flexible Log-MEP algorithm
- Multi-processor architecture, several throughput levels selectable before synthesis
- Dynamic iteration stopping feature for reducing average number of iterations
- On-the-fly change of block length, number of iterations, and selection of the Log-MAP algorithm
- Low latency
- No external memory required
Standard Deliverables
The TC7000-LTE core is delivered as a synthesized netlist. Deliverables include:
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RTL model simulation libraries
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MATLAB/C bit-true model
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Testbench VHDL source code
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Technical support and documentation
Contact Information
For additional information, contact TurboConcept at:
TurboConcept
40, rue Joseph Fourier
29280 Plouzane, France
Tel. +33 2 98 05 63 80
Fax +33 2 98 05 63 89
E-mail: info@turboconcept.com
http://www.turboconcept.com
