MPEG-2 Video Decoder (CS6651)
Features
- Supports progressive scan and interlaced streams
- ISO/IEC 13818-2 (H.262)-compliant
- Main profile at main level (MP@ML) compliant
- Decodes ISO/IEC11172-2 (MPEG1)
- Constrained parameter bitstreams
- High-performance solution for MPEG2 decoding
- Supports input bit rates up to 30 Mbps
- Real time decode and display of MP@ML using a single 27-MHz clock
- Supports PAL and NTSC standard definition television (SDTV) resolutions and frame rates
- Bitstream error detection and recovery
- Glueless interface to external SDRAM
- Capable of standalone stream decoding or host CPU-controlled operation
- Fully synchronous design with host shutdown and restart control
Block Diagram
Figure 1 shows the block diagram for the digital video broadcast (DVB) forward error correction (FEC) codec megafunction.
| Figure 1. MPEG-2 Video Decoder (CS6651) Block Diagram |
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Description
The CS6651 MPEG-2 decoder provides high-performance solutions for a broad range of motion image applications. This highly-integrated semiconductor intellectual property (IP), designed for standard definition video, is compliant with the ISO/IEC 13818-2 standard (MPEG-2), and is capable of decoding video streams at the MP@ML standard. The CS6651 is at home in mainstream consumer applications and can also decode MPEG-1 (ISO/IEC 11172-2) bitstreams.
The CS6651 accepts the input video elementary stream as aligned bytes from conditional access decryption, transport stream demultiplexer, or a similar source. The maximum average input bit rate is 30 Mbps. The core can operate in a default mode on an input stream without the intervention of a host CPU. In this mode, pictures will be decoded from the video stream and output in the correct display order. A host CPU has access to a full range of information and control to manipulate the behavior of the decoder to permit audio/video synchronization, pan-and-scan and letterbox conversion, and various trick modes. A highly configurable pixel stream direct memory access (DMA) engine provides the output from the core. This engine allows adjustable output video component sequencing and provides external logic with control over the display of the picture. To meet the bandwidth requirements of MP@ML decoding, a dedicated SDRAM chip is used. This is a commodity 64-Mbit SDRAM in 2M- by 32-bit configuration.
Applications for the CS6651 include:
- Digital cable and satellite set-top decoder box for SDTV
- DVD players
- PC video hardware accelerator
Device Utilization Example
Table 1 lists the typical device utilization results for the MPEG-2 decoder.
| Table 1. Typical Device Utilization |
| Target Device |
Speed Grade |
Utilization |
| Logic Elements (LEs) (1) |
Memory |
| Cyclone™ 1C20 |
-6 |
12,888 |
18 M4Ks |
| Stratix® 1S20 |
-5 |
9,894 |
10 M4K, 8 M512 |
| Stratix II 2S30 |
-3 |
7,957 |
10 M4K, 8 M512 |
Notes:
- The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
Contact Information
For additional information, contact Amphion Semiconductor, Ltd. at:
Headquarters and Engineering:
Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001
Email: info@amphion.com
URL: http://www.amphion.com
Amphion is a registered member of MPEG LA. Terms and conditions governing the MPEG-2 standard apply.
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