from Barco Silex
    |
Features
- Compliant with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
- 2D decomposition with a programmable number of decomposition levels from 0 (bypass) up to five
- Programmable lossless integer 5/3 or lossy floating point 9/7 filter
- Periodic symmetric border extension (according to JPEG2000 standard)
- Compact lifting scheme architecture with successive vertical and horizontal 1-D decompositions
- 16-bit data path; fixed-point 9/7 approximation
- Fully configurable tile size, from 1 x 1 pixel up to 128 x 128 pixels; configurable tile offset
- Internal tile buffer for increased performance
- Configurable pixel depth and sign up to 16 bits (almost limited to 12 bits in lossless; 10 bits in lossy)
- High-speed pixel interface, allowing transfer of 1 pixel per clock cycle on an entire tile
- Easy slave pixel interface through simple synchronous protocol
- Easy slave coefficient interface through direct read access to internal tile buffer (SRAM type) and simple addressing of resultant decomposed sub-bands in tile buffer
- Availability of used decomposition parameters at the coefficient interface for easing integration in a compression chain
- Efficient pipelined architecture
- Fully synchronous design for easing integration with provided multi-cycle definitions for increasing performance
- Single clock design
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. BA113FDWT Block Diagram
 |
 View full detail (104 KB) |
Description
Figure 1 illustrates a simplified block diagram of the BA113FDWT intellectual property (IP), showing the internal modules and the interfaces. The BA113FDWT IP is a tile-level 2-D discrete wavelet transform (DTW) engine decomposing a rectangular tile of any size up to 128 by 128 pixels into multiple frequency sub-bands. The BA113FDWT pixel interface can accept an entire tile at high speed with no interruption.
The IP core handles up to five multiple decompositions internally. It stores the resultant decomposed subbands into its internal tile buffer where data can be fetched via the coefficient interface by simply addressing the tile buffer. Decomposed data is arranged in an easy way to facilitate subband access. Each sub-band is separately accessible from the tile buffer.
In addition, access to the coefficient interface allows the parameters to be used for decomposing the tile, which correspond to the parameters specified at the global configuration interface. This eases the integration of the wavelet core into a processing chain where decomposition parameters are needed by the next process. This feature allows the decomposition parameters to change for processing the next tile and keeps the further processes in tune with the actual parameters used for a given tile.
Table 1 reports the efficiency results of the BA113FDWT IP core according to the number of decompositions; this represents the actual sample throughput achieved by the IP core compared to the clock frequency. This number depends on the requested number of decompositions because the filtering is recursively applied on each generated LL sub-band.
| Table 1. Throughput Efficiency | |
| # decomp | Efficiency |
|---|---|
| 0 | 96% |
| 1 | 96% |
| 2 | 76% |
| 3 | 72% |
| 4 | 71% |
| 5 | 70% |
The BA113FDWT core is driven by a global configuration interface, which allows you to set the various parameters (required for tile decomposition) and a simple command and control interface, which includes the start function and the ability to monitor the process. The following sections describe the modules constituting the BA113FDWT IP core, as shown in Figure 1.
Level Shifter and Data Router
The level shifter performs all operations needed to align the input pixels to the internal number format of the data path. This implies level-shifting, unsigned pixel data; and adding fractional bits for 9/7 fixed-point processing. The data router module reorders data before entering into the 1D vertical wavelet filter. It also manages multi-level decomposition by fetching intermediate LL sub-bands from the tile buffer.
1D Vertical and Horizontal DWT
Both modules perform a single-level 2-D wavelet decomposition. The first module achieves vertical decomposition on the tile columns, while the second module achieves horizontal decomposition on the tile lines. When combined, both processes result in bi-dimensional wavelet transforms. These modules feature a 16-bit data path. They implement a state-of-the-art periodic symmetric border extension according to the programmed tile size (compliant with JPEG2000).
Sequencer
This module organizes the internal BA113FDWT pipeline. It communicates with the host through a simple Command&Control interface allowing to start processing and to monitor the decomposition process. The BA113FDWT is driven at tile level and performs complete multi-level decomposition (storing the results into the internal tile buffer) before going back to idle state.
The module is configured by a static global configuration interface that fixes the various parameters to be used for decomposition.
Device Utilization and Performance
Table 2 lists the typical device utilization results for the megafunction.
| Table 2. Typical Device Utilization for the Megafunction | ||||||
| Target Device | Speed Grade | Utilization | Performance (fMAX) |
Parameter Setting | ||
|---|---|---|---|---|---|---|
| Logic Cells | Memory | I/O Pins | ||||
| Stratix® EP1S20F484C5 | -5 | 4,397 | 2 MRAM 24 M4K |
141 | 140 MHz | - |
| HardCopy® HC1s30-F780 | - | - | - | - | 155 MHz | - |
Deliverables
- Encrypted netlist w/ license file
- Data sheet
- Test bench
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com
