JPEG2000 Decoder
Features
- Compliance with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
- Support for lossless and lossy decompressions
- Parametric number of parallel entropy chains for improved compressed data throughput
- Dynamically configurable decoder parameters, including:
- Wavelet filter type: 5/3 or 9/7
- Number of wavelet recompositions from zero to five levels
- Tile size of up to 128 x 128 pixels and tile offset
- Code block size up to 32 x 32 samples
- Pixel depth of up to 12 bits in lossless mode (10 bits in lossy) pixel sign
- Entropy decoder with full support of JPEG2000 options
- One quantization factor per subband under mantissa/exponent format
- High-speed pixel interface allowing the transfer of one pixel per clock cycle on a whole tile component
- Easy interface-to-pixel output
- Compressed data input through simple synchronous protocol
- Decoder parameterization and control via synchronous host interface to external CPU
- Command and control interface for driving the decoder with limited or no CPU intervention
- Independent pixel and compressed interface clock domains for easy integration
- Fully synchronous design
- On-chip tile buffer for increased efficiency and reduced pinout
- Throughputs ranging from sub CIF 25 Hz to SDTV to HDTV 1280 x 720 50 Hz
Block Diagram
Figure 1 shows a block diagram of the megafunction.
Figure 1. Block Diagram
Description
Figure 1 illustrates a simplified block diagram of the BA111JPEG2000D intellectual property (IP) showing the internal modules and the interfaces. The BA111JPEG2000D IP is a tile-level decoder, processing each tile component independently from its neighbors. Tile components are rectangular areas of the source image. The size of the tile components depends on the partitioning of a given component plane; however, the size of the tile component processed by the IP core is dynamically configurable, with a limit of 128 x 128 pixels.
The JPEG2000 Decoder's process flow consists of these three steps:
- The IP core receives the compressed data interface. Each code stream represents code blocks of a given tile component of the image to reconstruct. The compressed data interface can then feature several channels in parallel.
- The IP core generates reconstructed pixels of the tile component at its pixel interface (with a throughput of one pixel per clock cycle) without any interruption throughout the entire tile component.
- Finally, if necessary, the pixel interface can be stalled by the peripheral device connected to it.
The decoder has a simple generic interface to an external CPU to configure the various parameters and to monitor the status of the decoding process.
Modeler and Arithmetic Decoder
The modeler gives the sequencing of the entropy decoding. It reconstructs the code block bit-plane by bit-plane, and places relevant bits in a zigzag pattern in each one. It also computes the context information that the arithmetic decoder needs. The contexts and input code stream that are read at the compressed interface are then processed by the arithmetic decoder. The decoder then generates the decoded bits that are placed in the correct location by the modeler.
Ancillary information, read at the compressed interface, specifies code-block coordinates and allows the IP core to locate the code blocks in the current tile component. This also allows several entropy channels to work in parallel.
The BA111JPEG2000D core features a configurable number of entropy decoders placed in parallel to sustain high decoding rates. Each entropy chain then processes a code block independently from neighbor chains.
Tile Composer
This unit reconstructs quantized sub-bands based on the code blocks coming from the entropy decoding channels. The tile composer module arbitrates between the available chains, gathering the various decoded code blocks. The tile composer reads the code blocks from local code block buffers.
Inverse Quantizer
The quantized sub-bands available from the tile composer are further processed by the inverse quantizer that applies a programmable inverse quantization step. A different inverse quantization step can be programmed for each sub-band, weighting lower-frequency sub-bands differently than higher-frequency ones. The inverse quantizer stores the resultant sub-bands into an on-chip tile buffer. The inverse quantizer can be bypassed for lossless mode.
2D Inverse Discrete Wavelet Transform
The last module of the IP core is the inverse discrete wavelet transform (IDWT) engine. This module processes tiles of pixels up to 128 x 128 pixels. The module performs bidimensional wavelet recomposition on the sub-bands located in the on-chip tile buffer, with up to five programmable recomposition levels. The wavelet transform can be programmed to be lossy, lossless, or bypassed. The IDWT module generates reconstructed pixels of any size up to 12 bits (10 for lossy) at the pixel interface. It performs level shifting as required by the JPEG2000 standard.
Host Interface Module
This module allows the IP core to interface with a CPU. It contains configuration registers for the various modules and gives status information about the decoding progress. An active-low interrupt line signals selectable events during the decompression process. The host interface module also features a separate command and control interface that allows fast control of the IP core with minimal or no CPU intervention. Together, with the simplicity of the CPU interface, the command and control interface allows you to build a system where the BA111JPEG2000D IP core is not directly connected to a host CPU and is driven by a small amount of logic. This increases the integration flexibility of the IP core.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
Memory |
I/O Pins |
| EP1S30FC780C5 |
-5 |
24,950 |
2 |
262 |
97 MHz |
8 channels |
| HC1S40F780 |
HardCopy®
Structured ASIC |
- |
- |
- |
138 MHz |
8 channels |
| EP1S20FC484C5 |
-5 |
8,372 |
2 |
122 |
111 MHz |
1 channel |
| HC1S40F780 |
HardCopy
Structured ASIC |
- |
- |
- |
160 MHz |
1 channel |
Deliverables
- Encrypted netlist with license file
- Data sheet
- Testbench
Related Links
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com
|
Literature
> 
View full detail (138KB)
