JPEG2000 Encoder
Features
- Compliance with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
- Support for lossless and lossy compressions
- Parametric number of parallel entropy chains for improved compressed data throughput
- Rate and distortion metrics provided for rate allocation (tier 2)
- Dynamically configurable encoder parameters, including:
- Wavelet filter type: 5/3 or 9/7
- Tile size up to 128 x 128 pixels and tile offset
- Code block size up to 32 x 32 samples
- Pixel depth of up to 12 bits in lossless mode (10 bits in lossy) pixel sign
- Entropy encoder with full support of JPEG2000 options
- One quantization factor per sub-band under mantissa/exponent format
- High-speed pixel interface allowing the transfer of 1 pixel per clock cycle on an entire tile component
- Easy interface-to-pixel input
- Compressed data output through simple synchronous protocol
- Encoder parameterization and control via synchronous host interface to external CPU
- Command and control interface for driving the encoder with limited or no CPU intervention
- Independent pixel and compressed interface clock domains for easy integration
- Fully synchronous design
- On-chip tile buffer for increased efficiency and reduced pinout
Block Diagram
Figure 1 shows a block diagram of the megafunction.
Figure 1. JPEG2000 Encoder
Description
Figure 1 illustrates a simplified block diagram of the BA112JPEG2000E intellectual property (IP) showing the internal modules and the interfaces. The BA112JPEG2000E IP is a tile-level encoder processing each tile component independently from its neighbors. Each color component of the source image is encoded separately and is decomposed into tile components, or rectangular tiles of 128 x 128 pixels maximum, to be read by the encoder. The BA112JPEG2000E pixel interface can accept an entire tile component at a high speed without any interruption. It generates the compressed codes at its compressed data interface (featuring several channels in parallel) with distortion and rate metrics, which can then be used for tier 2. This enables precise control of the bit rate by the CPU, and the various progressive order modes foreseen in the standard. The encoder has a simple generic interface to an external CPU to configure the various parameters the IP core can handle and to monitor the status of the encoding process.
The following sections describe the modules of the BA112JPEG2000E IP core as depicted in Figure 1.
2D Discrete Wavelet Transform
The first module of the core is the discrete wavelet transform (DTW) engine. This module accepts tiles of up to 128 x 128 pixels and performs bidimensional wavelet decomposition on the incoming data with up to five decomposition levels. The wavelet transform can be programmed to be lossy, lossless, or bypassed. The DWT module accepts incoming pixels of up to 12 bits (10 for lossy) and performs level-shifting as required by the JPEG2000 standard. It finally stores its results into the on-chip tile buffer, ready for quantization and code block decomposition.
Quantizer
The quantizer fetches the sub-bands available from the tile buffer and applies a programmable quantization step. A different quantization step can be programmed for each sub-band, allowing lower-frequency sub-bands to weight differently than higher-frequency ones. The quantizer can be bypassed for lossless mode.
Tile Splitter
This unit divides the quantized sub-bands into rectangular code blocks of up to 32 x 32 samples to make them ready for entropy encoding. The BA112JPEG2000E IP core features a configurable number of entropy encoders placed in parallel configuration to sustain high encoding rates. Each entropy chain processes a code block independently from neighbor chains. The tile splitter module arbitrates between the available chains, dispatching the various code blocks to be encoded. The tile splitter stores the code blocks into local code block buffers.
Modeler and Arithmetic Encoder
The modeler performs the first part of the entropy encoding. It parses the code block bit-plane by bit-plane, from most significant bit (MSB) to least-significant bit (LSB) and places relevant bits in a zigzag pattern in each bit plane. It also computes the context information that the arithmetic decoder needs. The distortion metrics are then available at the compressed interface to be used for the tier-2 part of the JPEG2000 algorithm. Distortion is based on an MSE criterion and measures the amount of error introduced by truncating the code block at each truncation point. The bits and contexts are then processed by the arithmetic encoder that generates the stream available at the compressed interface. Ancillary information reporting code-block coordinates allows the tier 2 encoder to re-order the output of the entropy channels.
Host Interface Module
This module allows the IP core to interface with a CPU. It contains configuration registers for the various modules and gives status information about the encoding progress. An active-low interrupt line signals selectable events during the compression process. The host interface module also features a separate command and control interface that allows fast control of the IP core with minimal or no CPU intervention. Together, with the simplicity of the CPU interface, the command and control interface allows you to build a system where the BA112JPEG2000E core is not directly connected to a host CPU and is driven by a small amount of logic. This increases the integration flexibility of the IP core.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
Memory |
I/O Pins |
| EP1S30FC780C5 |
-5 |
23,372 |
2 MRAM
124 M4K |
542 |
114 MHz |
8 channels |
| HC1S40F780 |
HardCopy® Structured ASIC |
- |
- |
- |
140 MHz |
8 channels |
| EP1S20FC484C5 |
-5 |
9,445 |
2 MRAM
40 M4K |
157 |
118 MHz |
1 channel |
| HC1S40F780 |
HardCopy Structured ASIC |
- |
- |
- |
140 MHz |
1 channel |
Deliverables
- Encrypted netlist with license file
- Data sheet
- Testbench
Related Links
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
Email: barco-silex@barco.com
URL: www.barco-silex.com
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