from Barco Silex
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Features
- Sub-frame latency decoding (<5 ms)
- Full-image decoding (no tiling)
- Compliant with JPEG 2000 (ISO/IEC 15444-1)
- Integrated intellectual property (IP) core for JPEG 2000
- Single FPGA solution:
- High definition (HD): 720p30-180, 1080i30-180, 1080p30-90
- Digital Cinema Initiatives (DCI): 2K, 4K
- Custom frame sizes: up to 8k or larger
- Customizable input bit rate: up to 200 Mbps or 400 Mbps
- YUV 4:2:2 color space
- Supports the following JPEG parameters:
- Pixel depth: up to 12 bits per color sample
- Full-frame decoding (no tiling)
- Fully autonomous decoder with automatic parameter extraction
- Minimal user intervention
- Fully synchronous design
- Supports FPGA and ASIC technologies
- Integrates with Barco Silex cryptography cores for advanced stream protection
Block Diagram
Figure 1 shows a block diagram of the MegaCore® function.
Description
Capitalizing on its long-term experience with JPEG 2000 hardware coding, Barco Silex offers a large JPEG 2000 portfolio including this compact, real-time hardware decoder engine that is optimized for low-latency video applications. The core architecture offers a flexible and high-speed solution to meet the challenges of high-end broadcast applications. The BA129 is able to sustain up to 180 frames per second (fps) of 1080i format, for compressed stream bit rates extending up to 400 megabits per second (Mbps).
The BA129 core decodes streams that are compliant with the ISO/IEC 15444-1 specification (JPEG 2000) and supports single-tiled frames up to 1080p or larger. The BA129 is the complement of the BA130 sub-frame latency JPEG 2000 encoder IP, to which it can be directly connected.
The IP core performs the complete video decompression operations of the normalized decoding process:
- Stream parsing and header decoding
- Entropy decoding
- Inverse quantization
- Inverse discrete wavelet transform (IDWT)
The BA129 takes a JPEG 2000 file and generates decoded samples as its output interface with up to 12 bits per color sample. An optional module can be used to generate the video output in real-time, without any buffering, to preserve the low-latency performance.
The BA129 IP provides a single-FPGA solution for 720p30-180, 1080i30-180 and 1080p30-90 video modes, with a total pixel-to-pixel latency below 9 ms for 1080i/p60, below 5 ms for 1080i/p120 and below 3 ms for 1080i/p180 when used together with the BA130 encoder.
The flexible FPGA architecture allows you to build a secure decoder by integrating Barco Silex cryptography IP cores.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the MegaCore function.
| Table 1. Typical Device Utilization for the MegaCore Function | ||||||
| Resolution | Configuration | Frame Rate | Bandwidth | Minimum Target Device | ||
|---|---|---|---|---|---|---|
| 720p60 | 1 channel 1280x720 YUV 4:2:2, 10 bits |
60 fps | 200 Mbps | Stratix® III E80 or L110 FPGA Arria® II GX 95 FPGA All Stratix IV and Stratix V FPGAs |
||
| 1080p30 | 1 channel 1920x1080 YUV 4:2:2, 10 bits |
30 fps | 200 Mbps | Stratix III E80 or L110 FPGA Arria II GX 95 FPGA All Stratix IV and Stratix V FPGAs |
||
| 1080p60 | 1 channel 1920x1080 YUV 4:2:2, 10 bits |
60 fps |
400 Mbps |
Stratix III E110 or L150 FPGA Arria II GX 125 FPGA All Stratix IV and Stratix V FPGAs |
||
| 2K | 1 channel 2048x1080 RGB 4:2:2, 12 bits |
24 fps |
250 Mbps |
Stratix III E80 or L110 FPGA Arria II GX 95 FPGA All Stratix IV and Stratix V FPGAs |
||
Deliverables
- Design encrypted files
- VHDL testbenches
- VHDL instantiation templates
- Altera® Quartus® II implementation example
- User guide
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com
