H264-MCE Multi-channel HDTV H.264/AVC Baseline Video Encoder Megafunction
Features
- Fully compatible with the ITU-T H.264 baseline specification, profile level 4.1
- Supports the entire range of common video resolutions with very low operational frequencies. For example:
- SXGA progressive (1280×1024) at 30 frames per second (fps) requires about 157 MHz
- 720p HDTV progressive (1280×720) at 30 fps requires about 110 MHz
- VGA (640×480) at 30 fps requires about 37 MHz
- NTSC CIF (352×240) at 30 fps requires about 12 MHz
- NTSC QCIF (176×120) at 15 fps requires about 1.5 MHz
- Supports up to 32 frame-multiplexed video channels; each may have a different resolution and frame rate
- Independent hardware encoder processes video without assistance of a microprocessor
- Supports YCbCr 4:2:0 16x16 block video input
- Flexible output:
- Constant bit rate (CBR) for applications with limited bandwidth
- Variable bit rate (VBR) for low latency and detailed images in fast-changing scenes
- Motion vector up to –16.00/+15.75 pixels (search area is 32x32 pixel wide down to a quarter pixel)
- Supports most intra 4×4 and all intra 16×16 modes
- Supports multiple slices for better error resilience
- Single slice support for Main profile decoders
- Block skipping logic for lower bit rate
- Very low latency in VBR mode (~1 ms for VGA at 30 fps)
- Deblocking filter for better quality, especially at low bit rates
- Flexible external memory interface is tolerant to high latencies and delays (ideal in a SoC system or in a shared bus with a CPU) and can be clocked at a different frequency from the megafunction for easier integration
- Independent of memory type; works with SRAM, SDRAM, or DDRAM
- Minimum clock speed is four times the raw pixel clock speed
- Simple, fully-synchronous design
Block Diagram
Figure 1 shows a block diagram of the H264-MCE Encoder.
Figure 1. H264-MCE Encoder
 Click for full detail (33KB)
Description
The H264-MCE implements an independent hardware encoder for the H.264 Advanced Video Coding (AVC) Baseline profile video compression algorithm (level 4.1). It can process up to 32 frame-multiplexed video channels, and each channel can have its own resolution and frame rate. Designed for high-quality output, performance and area efficiency, and application flexibility, the megafunction can encode video from QCIF resolution for mobile phones (176×120 pixels) at 15 fps all the way up to SXGA (1280×1024 pixels, progressive) at 30 fps.
The megafunction features a simple, flexible, 32-bit external memory interface that makes the megafunction independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant of the large delays and latencies typical of a shared bus architecture such as AMBA™. The interfaced memory can also operate at a different speed than the megafunction itself, saving considerable resources and making the megafunction well-suited for a SoC implementation where the bus is typically shared with the CPU and other megafunctions.
The megafunction supports multiple slices, helping to protect the encoded image from transmission error damage and giving the megafunction an error resiliency useful in challenging environments. It also offers a deblocking filter and macroblock skipping, two features important for low data rates. Highly flexible, the megafunction can be configured for one-slice video encoding, making its output suitable for the Main profile decoders typical of digital television applications.
Implementation results show the megafunction is competitively area-efficient in ASICs and also suitable for most FPGA devices. 4CIF (704×576) at 30 fps is supported in the slowest speed grade of low-end FPGAs, and high-end FPGAs can reach 720p (1280×720) at 30 fps. The simple design is fully synchronous, and SoC integration is straightforward. A complete verification environment helps designers verify the functioning of the megafunction.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
|
Target Device
|
Speed Grade |
Utilization |
Performance
(fMAX) |
| Resources |
Embedded Array Block |
I/O Pins |
| Cyclone® II EP2C35 |
-6 |
20,058 LEs (1) |
64 M4K |
280 |
76 MHz |
| Stratix® II EP2S30 |
-3 |
18,551 ALMs (2) |
57 M4K |
280 |
118 MHz |
| HardCopy® II HC210 |
-1 |
128,978 HCells (3) |
62 M4K |
280 |
177 MHz |
Notes to Table 1:
- Cyclone II device design includes logic elements (LEs).
- Stratix II devices use adaptive look-up modules (ALMs).
- HardCopy II devices feature structured cells (HCells).
Deliverables
- EDIF netlist
- Assignment and configuration
- Symbol file
- Include file
- Vectors for testing the functionality of the megafunction including expected results
- Documentation
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
Tel: (201) 391-8300
Fax: (201) 391-8694
Email: info@cast-inc.com
URL: www.cast-inc.com
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