JPEG-D Decoder

from CAST, Inc.

Features

• Baseline ISO/IEC 10918-1 JPEG compliance
  • Programmable Huffman tables (two DC, two AC)
  • Programmable quantization tables (four)
  • Up to four color components (optionally extendable to 255 components)
  • Supports all possible scan configurations and all JPEG formats for input/output data
  • Supports any image size up to 64k x 64k
  • Supports DNL and restart markers

• Additional image processing capabilities
  • Motion JPEG decoding
  • Decompressing at various resolutions via downscaling in the frequency domain (optional)
• Designed for easy integration
  • Stand-alone operation
  • Automatic self-programming by JPEG stream headers parsing
  • Header errors catching
  • Broadcasting of decoded image parameters for controlling peripherals such as a raster to block converter
• Designed for high quality
  • Robust verification environment includes bit-accurate software model
  • ASIC- and FPGA-proven in multiple designs
  • Scan-ready design architecture

Block Diagram

Figure 1. Block Diagram of the Function

 Click for full detail (94.92 KB)

Description

Implements a high-performance image or video decoder that complies with the baseline ISO/IEC 10918-1 JPEG standard.

One of the fastest available JPEG megafunctions, the JPEG-D provides a high-performance solution for a variety of image and video decompression applications. It can, for example, decode 16:9 HDTV, 1920 x 1152, 4:2:0.

In addition to processing baseline JPEG streams, the megafunction can decompress non-standard motion JPEG streams. It can also be enhanced with an optional IDCT block that enables down-scaling in the frequency domain, a feature that allows decompression at various resolutions from the same compressed stream.

The megafunction includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces, such as AMBA, are also available. The megafunction is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system-on-chip verification.

Device Utilization and Performance

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

• Post-synthesis electronic design interchange format (EDIF) netlist
• Symbol file
• Sophisticated high-level data link (HDL) testbench
• Simulation script, vecStors, expected results, and comparison utility
• Software (C++) bit-accurate model
• Comprehensive user documentation (including detailed specifications) and a system integration guide

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
Tel: (201) 391-8300
Fax: (201) 391-8694
Email: info@cast-inc.com
URL: www.cast-inc.com