JPEG-E Encoder
Features
- Supports Altera® Cyclone®, Stratix®, and HardCopy® series devices
- Baseline ISO/IEC 10918-1 JPEG compliance
- Programmable Huffman tables (two DC, two AC)
- Programmable quantization tables (four)
- Up to four color components (optionally extendable to 255 components)
- Supports all possible scan configurations and all JPEG formats for input/output data
- Supports any image size up to 64k x 64k
- Supports DNL and restart markers
- Additional image processing capabilities
- Motion JPEG encoding
- Rate-control (optional)
- Designed for easy integration
- Single clock per input sample for encoding
- Fully programmable through standard JPEG stream marker segments
- Automatic headers generation
- Automatic program-once, encode-many operation
- Designed for high quality
- Robust verification environment includes bit-accurate software model
- ASIC and FPGA proven in multiple designs
- Scan-ready design architecture
Block Diagram
Figure 1. Block Diagram of the Function
 Click for full detail (94 KB)
Description
The JPEG-E megafunction Implements a high-performance image encoder that compiles with the baseline ISO/IEC 10918-1 JPEG standard.
One of the fastest available JPEG megafunctions, the JPEG-E megafunction provides a high-performance solution for a variety of image and video compression applications. It can, for example, encode over 30 frames per second for 4:3 HDTV, 1440 x 1152, and 4:2:0.
In addition to processing baseline JPEG streams, the JPEG-E megafunction can compress non-standard motion JPEG streams. It can also be enhanced with an optional add-on bit-rate control block, which may benefit applications that have tight bandwidth constraints.
The JPEG-E megafunction includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces, such as AMBA, are available. The megafunction is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system-on-chip verification.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
| Logic Cells |
Embedded Array Blocks |
I/O Pins |
| EP1C12 |
-6
|
7,201 LEs
|
9 M4Ks
|
79
|
125 MHz
|
| EP2C20 |
-6
|
5,337 LEs
|
9 M4Ks, 19 DSP-9bit
|
79
|
154 MHz
|
| EP3C16 |
-6
|
5,259 LEs
|
7 M9Ks, 19 DSP-9bit
|
79
|
161 MHz
|
| EP1S10 |
-5
|
5,389 LEs
|
8 M4Ks, 1M512, 18 DSP-9bit |
79
|
143 MHz
|
| EP2S15 |
-3 |
4,519 ALUTs |
8 M4K; 1M512, 18 DSP-9bit |
79 |
229 MHz |
| EP3SE50 |
-2 |
4,429 ALUTs |
7 M9Ks; 15 DSP-18bit |
79 |
250 MHz |
| HC210 |
- |
55,310 HCells |
9 M4K; 18 DSP-9bit |
79 |
238 MHz |
Deliverables
- Post-synthesis electronic design interchange format (EDIF) netlist
- Symbol file
- Sophisticated high-level data link (HDL) testbench
- Simulation script, vecStors, expected results, and comparison utility
- Software (C++) bit-accurate model
- Comprehensive user documentation, including a detailed specification and a system integration guide
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
Tel: (201) 391-8300
Fax: (201) 391-8694
Email: info@cast-inc.com
URL: www.cast-inc.com
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