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Commsonic DVB-T Modulator

Home > Products > Intellectual Property > DSP > Modulation & Demodulation > Commsonic DVB-T Modulator

from Commsonic

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AMPP Approved
OpenCore Support
SOPC Builder Ready



Features

  • Randomizer
  • Reed Solomon encoder
  • Outer interleaver
  • Convolutional encoder
  • Inner interleaver
  • QAM mapper
  • Framing and pilot insertion
  • Inverse FFT
  • Guard interval insertion
  • Fixed or variable bandwidth interpolation (optional)
  • External DDS interface (e.g., AD9857) (optional)
  • Baseband to IF conversion (optional)
  • Inverse SINC filter for DAC aperture correction (optional)
  • Flexible radio interface (optional)

Block Diagram

Figure 1 shows a block diagram of this megafunction.

Figure 1. CMS0009 DVB-T Modulator Block Diagram

Figure 1. CMS0009 DVB-T Modulator Block Diagram

Adobe Acrobat IconClick for full detail

Description

The proliferation of low-cost DVB-T demodulation and set-top-box products has opened up a wealth of opportunities for applications requiring low-cost broadband wireless audio/video/data links. Commodity products have largely been aimed at the broadcast market where high volumes are at the demodulation end of the link. The Commsonic DVB-T Modulator allows exploitation of this technology by allowing the development of the modulator in low-cost FPGA implementation. Applications include CCTV, wireless home networking, and test equipment.

This core is intended to provide a very efficient FPGA or ASIC implementation of all functions required to take the output from an MPEG-2 transport multiplexer and modulate it according to ETSI EN300 744 v1.4.1. The specification is fully supported for 2K and 8K COFDM modes as well as hierarchical transport streams. The standard output is a baseband I/Q digital pair for direct connection to a DAC. Alternative output configurations include a low IF or direct connection to standard Analog Devices Direct Digital Synthesizers (e.g., AD9857).

DVB-T(H) 4k and interleaver extension is also available.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for Altera Megafunctions 
Target Altera®  Device Speed Grade Logic Elements (LEs) M4K Blocks DSP Blocks Performance (fMAX) Parameter Setting
EP2C20 -8 5K 49 14 64 MHz 2K-OFDM
EP1S10 -7 6K 22 (+1 MRAM, 6xM512) 14 64 MHz 2K, 8K-OFDM
EP2S30 -5 5K 22 (+1 MRAM, 6xM512) 14 64 MHz 2K, 8K-OFDM

Deliverables

  • Core encrypted VHDL for Quartus® II software
  • Testbench pre-compiled simulation libraries for ModelSim® tool
  • VHDL test scripts
  • Documentation user guide
  • One year of technical support and maintenance

Contact Information

For additional information, contact Commsonic at:

Commsonic Limited
St Johns Innovation Centre
Cowley Road
Cambridge CB4 0WS
ENGLAND
Tel: +44(0)1223 421845
Fax: +44(0)1223 871071
Email: info@commsonic.com
URL: www.commsonic.com

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