Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
   DSP
          Filtering
          Modulation/Demodulation
          Transforms
          Encryption/Decryption
          Error Detection/Correction
          Video & Image Processing
          Audio Processing
          Arithmetic
          Signal Generation
          Additional Functions
          Consortiums
          Literature
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

FFT/IFFT High Performance 64-Point

from Amphion Semiconductor, Ltd.

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • High performance
  • No external memory required
  • Easy to use

Block Diagram

Figure 1 shows the block diagram for the Amphion high performance 64-point fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) megafunction.

Figure 1. FFT/IFFT High Performance 64-Point Block Diagram
Figure 1. FFT/IFFT High Performance 64-Point Block Diagram

View Full Size

Description

The Amphion high performance 64-point FFT/IFFT megafunction, FFT64HP, performs forward or inverse FFT functions on complex data containing 64 points according to the equations below:

Equations

Data is loaded into the workspace RAM in normal sequential order. The transformed data comes out from the function in radix-4 digitally-reversed order with the index indicated by output QIX.

The FFT64HP megafunction is based on the radix-4 decimation in frequency (DIF) algorithm. It performs the computation concurrently in three highly pipelined cascaded stages, as illustrated in Figure 29. The FFT64P megafunction is capable of processing continuous input data and contains all the necessary circuits to support this continuous processing.

The internal complex programmable logic device (CPLD) memory is utilized and the whole circuit is on a single device. Both the input and output are complex numbers in the two’s complement format. The input wordlength is 9 bits and the output wordlength is 12 bits. The twiddle factors and internal commutation data wordlengths are 12 bits.

The function can accept continuous input data, i.e., a 64-point data block every 64 clock cycles. When clocked at 54 MHz, the function achieves continuous computation speed of approximately 1.19 ms. The computation has a latency of 174 clock cycles.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
Logic Cells EABs (1)
EPF10K100ARC -1 3,963 12 13.88ns,
72 MHz
Contact Amphion

Note:

  1. EABs = Embedded array blocks

Contact Information

For additional information, you can contact Amphion Semiconductor, Ltd. at:

Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001

Email: info@amphion.com
URL: http://www.amphion.com  

  Please Give Us Feedback