from Barco Silex
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Features
- Optimized for APEX™ 20KC and APEX II architectures
- Combined fixed-point 2D DCT/IDCT core
- Row column decomposition method (RCM)
- Compatible with JPEG, H.263, and MPEG standards
- IDCT compliant to IEEE 1180-1990 number precision standard
- 9-bit signed (2's complement) pixel interface
- 12-bit signed (2's complement) transformed coefficient interface
- Deeply optimized architecture with small LE count
- One pixel per clock cycle throughput
- Continuous pipeline decoding across multiple consecutive blocks until end-of-data signaling
- Fully synchronous design with single clock
- Integrated dual-port 64 x 22 synchronous SRAM for block transposition
- Fully RTL design
- Simple synchronous strobe-acknowledge pixel and transformed coefficient interfaces
- End-of-image and end-of-scan support for easy integration in JPEG chains
Block Diagram
Figure 1 shows a block diagram of the megafunction.
| Figure 1. Block Diagram |
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Description
The bidirectional DCT/IDCT IP core performs high-speed 2D discrete cosine transform and inverse discrete cosine transform, dealing with 9-bit signed pixels and 12-bit signed transformed coefficients. This IP core efficiently decomposes 2D transforms into two consecutive 1D transforms with an effective 1-pixel per clock cycle throughput.
This IP core's internal arithmetic architecture has been tuned to meet the requirements of the IEEE 1180-1990 number precision standard with the smallest core area, allowing you to use this IP core for JPEG, H.263, and MPEG applications. This IP core features 12-bit unsigned cosine coefficients and 22-bit transpose memory.
With its simple synchronous interfaces and 100% synchronous structure, you can integrate this IP core in a complex system with little effort.
Contact Barco Silex for more information.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization | ||||||||
| Target Device | Speed Grade | Utilization | Performance (fMAX) |
Parameter Setting | ||||
|---|---|---|---|---|---|---|---|---|
| Logic Cells | ESBs | I/O Pins | ||||||
| EP20K200CQ208 | -7 | 3372 | 2 | 37 | 85 MHz | Contact Barco Silex | ||
| EP2A15F672C | -7 | 3371 | 2 | 37 | 97 MHz | Contact Barco Silex | ||
| EP1M120F484C | -5 | 3203 | 2 | 37 | 103 MHz | Contact Barco Silex | ||
Deliverables
- Design encrypted files
- VHDL testbenches
- Bit-level precise C models for DCT/IDCT functionalities
- VHDL/Verilog instantiation templates
- User guide documentation
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-selix@barco.com
URL: www.barco-silex.com
