FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

FFT MegaCore Function

Home > Products > Intellectual Property > DSP > Transforms > FFT MegaCore Function

from Altera Corporation

View Literature
Download Free Evaluation



OpenCore Plus Support
DSP Builder Ready



Features and Description

The fast Fourier transform (FFT) MegaCore® function is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.

The FFT MegaCore function accepts, as input, a complex data vector of length N (in two’s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.

The FFT MegaCore function has the following options:

  • Radix-4 and mixed radix-2/4 implementations
  • Variable transform length 
  • Block floating-point architecture—maximizes internal signal dynamic range
  • Use of internal memory

The FFT MegaCore also:

  • Is optimized to use digital signal processing (DSP) blocks and TriMatrix memory architecture
  • Uses embedded multipliers
  • Has intellectual property (IP) functional simulation models for use in Altera supported VHDL and Verilog HDL simulators

IP Evaluation

Use the Altera® OpenCore Plus Evaluation flow to test drive this MegaCore function.

Performance and Resource Utilization

Typical expected performance and utilization figures for this MegaCore function are provided in the FFT MegaCore Function User Guide (PDF).

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system.

Related Documents

  • FFT MegaCore Function User Guide (PDF)
  • MegaCore IP Library Release Notes and Errata (PDF)
Rate This Page


  • IP & Reference Designs
    • All Intellectual Property
    • All Reference Designs
    • Bridges & Adapters
      • Memory Mapped
      • Streaming
    • DSP
      • Filters & Transforms
      • Error Detection/Correction
      • Modulation & Demodulation
      • Video & Image Processing
    • Embedded Processors
      • Nios II
        • Processor Cores
          • Fast CPU
          • Economy CPU
          • Standard CPU
        • Benefits
          • Low Cost
          • High Performance
          • Long Life Cycle
          • Flexibility
        • Software Tools
          • Nios II IDE
          • Nios II C2H Compiler
          • Software
        • Development Kits
        • End Markets
        • Customer Successes
        • Literature
      • 32/16-Bit Microprocessors
      • 8/4-Bit Microprocessors
    • Interface Protocols
      • Communications
      • Ethernet
      • High Speed
      • PCI
      • Serial
      • Audio & Video
    • Memory Controllers
      • DMA
      • Flash
      • On-Chip
      • SDRAM
      • SRAM
    • Peripherals
      • Debug & Performance
      • Display
      • Microcontroller Peripherals
      • Multiprocessor Coord.
  • About IP
    • Designing with IP
      • IP Base Suite
    • Evaluate and Download IP
    • IP Certifications
    • System Design
    • Request IP
  • IP Partners
    • About AMPP Program
    • List of IP Partners
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates