- Host controller for SDIO, SD memory card, and MMC interface
- Allows host CPU to access SD and MMC devices
- Simple user interface optimized for on-chip bus connection
- User interface supports 32-bit and 64-bit data
- Option to integrate with other CPU bus slaves to support direct access by various CPUs including PowerPC, MPC680, ARM®, SH2/3/4, MIPS, and ARC microprocessors
- Supports SDIO direct memory access (DMA) operation for high-speed data transfer
- Supports SD host controller standard register set
- Fully programmable access timing
- Hardware support of cyclic redundancy code (CRC) error detection and interrupt generation
- Supports multi-function SD cards, command suspend, resume, and block transfer
- Option to operate the user interface and card interface at different clock domains
- Direct mapping of the host address space to card address space
- Fully static design with edge triggered flipflops
Figure 1. Block Diagram
The EP550 is a host controller for the SD memory card, SDIO, and MMC interface. The core connects the host CPU of the system to the SD card socket. External SD cards can be accessed by the host CPU through the EP550 controller core intellectual property (IP).
SD memory and SDIO are low-cost, high-speed interfaces designed for removable mass storage and IO devices. It is a very flexible architecture supporting variable clock rate and 1- to 4-bit SD data width. Data rates of up to 25 Mbytes/sec (200 Mbps) can be realized with the SD interface. Features such as plug and play, auto-detection, error correction, and write protection are standard with the SD interface.
The EP550 SD card host controller core is designed according to the SD Association's SD host controller specification. The core presents a very simple view of the SD card to the system software. All accesses to the SD card are made through the standard control register set. Direct memory access (DMA), burst access, cyclic redundancy code (CRC) error detection, interrupt, and timing are supported by the controller core. Given its standard register set, you can use the EP550 to replace other existing SD controllers with no change to system software.
There are several options for user hardware interface to the controller core. The controller supports a generic user interface optimized for on-chip logic, as well as an embedded CPU interface such as AMBA AHB bus. To access the SD card, the host CPU simply issues read/write access to the control registers in the core. The controller core handles all the SD card protocols automatically including data shifting, timing, and CRC generation. The core has a built-in DMA controller so that data can be automatically transferred between the system and the SD card without CPU intervention.
With the EP550, SD card interface can be realized with very little development cost. You can add SD memory and SDIO interfaces to the system by simply adding the EP550 module.
The EP550 implements the standard SD host controller register set, which allows you to use standard SDIO software development tools for system development. The EP550 also supports the SDIOWorx embedded SDIO stack/bus driver from embWiSe Technologies.
Device Utilization Example
Table 1 lists the typical device utilization results for the EP550.
|Table 1. Typical Device Utilization for the EP550|
|Speed Grade||Logic Cells||Memory||Performance (fMAX)|
|Cyclone® III||-7||2,535 LEs (1)||8K memory bits||81 MHz|
|Stratix® III||-3||1,912 ALMs (2)||8K memory bits||97.9 MHz|
- Netlist including routing and timing constraint file
- Testbench and simulation models
- Synthesis scripts
- Top-level design template
- Source code for bus driver development
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