Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
          Peripherals
          PCI
          PCI Express
          Memory Controllers
          USB
          PCMCIA
          Ethernet
          I2C
          CAN
          PowerPC Bus
          HyperTransport
          RapidIO
          SerialLite
          Additional Functions
          Consortiums
          Literature
   DSP
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

Nios II Advanced CAN

from IFI

Request Free Evaluation



AMPP Approved
OpenCore Support
SOPC Builder Ready



Features

The Nios® II Advanced CAN bus core includes the following features:

  • CAN 2.0B
  • Up to 256 message transmit buffer
  • Up to 256 message receive buffer
  • Up to 256 message filters
  • Nios II embedded processor interface
  • Silent mode
  • High priority messages
  • Time stamp

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. Advanced-Can Block Diagram

Figure1. Advanced-Can Block Diagram

Figure 1 Advanced-Can Block DiagramView full detail (180 KB)

Description

  • Small but efficient CAN controller
  • Easily integrated into Nios II systems using SOPC Builder
  • Avalon® interface for Nios II processor
  • Royalty free
  • Software drivers shipped with IP
  • Verified on Nios II development board
  • Evaluation version available
  • Software examples included

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization
Target Device

Utilization Logic
Elements (LEs) (1)

M4K Memory blocks I/O Pins
Cyclone™  FPGA 1350 3 -24 3
Cyclone II FPGA 1350 3 -24 3
Stratix® FPGA 1350 3 -24 3
Stratix II FPGA 1350 3 -24 3

Note:

  1. The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.

Contact Information

For additional information, contact:

Ingenieurbüro Für IC-Technologie
Kleiner Weg 3
97877 Wertheim
GERMANY
Tel: +49/9342/96080
Fax: +49/9342/5381
Email: ifi@ifi-pld.de
URL: www.ifi-pld.de

  Please Give Us Feedback