Nios II Advanced CAN
Features
The Nios® II Advanced CAN bus core includes the following features:
- CAN 2.0B
- Up to 256 message transmit buffer
- Up to 256 message receive buffer
- Up to 256 message filters
- Nios II embedded processor interface
- Silent mode
- High priority messages
- Time stamp
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. Advanced-Can Block Diagram
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Description
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Small but efficient CAN controller
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Easily integrated into Nios II systems using SOPC Builder
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Avalon® interface for Nios II processor
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Royalty free
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Software drivers shipped with IP
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Verified on Nios II development board
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Evaluation version available
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Software examples included
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization |
| Target Device |
Utilization Logic
Elements (LEs) (1)
|
M4K Memory blocks |
I/O Pins |
| Cyclone™ FPGA |
1350 |
3 -24 |
3 |
| Cyclone II FPGA |
1350 |
3 -24 |
3 |
| Stratix® FPGA |
1350 |
3 -24 |
3 |
| Stratix II FPGA |
1350 |
3 -24 |
3 |
Note:
- The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.
Contact Information
For additional information, contact:
Ingenieurbüro Für IC-Technologie
Kleiner Weg 3
97877 Wertheim
GERMANY
Tel: +49/9342/96080
Fax: +49/9342/5381
Email: ifi@ifi-pld.de
URL: www.ifi-pld.de
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