Triple-Speed Ethernet MegaCore Function
from Altera Corporation
Ethernet continues to evolve and adapt to new demands placed on the technology from new physical media. Gigabit Ethernet is now pervasive and supports both copper and optical transmission media.
Legacy systems require a smooth migration from 10 Mbps to 100 Mbps to 1000 Mbps. Altera’s Triple-Speed Ethernet MegaCore® function eases this migration path by providing a proven solution validated by the University of New Hampshire Interoperability Lab (UNH-IOL).
Features
- Complete 10/100/1000-Mbps Ethernet solution including:
- Media access controller (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) intellectual property (IP) modules
- Ethernet driver software and TCP/IP stack
- Development boards
- Reference designs
- Compliant to IEEE802.3 standard
- Successfully validated at UNH-IOL
- Logic element (LE) count as low as 900 (with small-MAC option)
- Optimized multi-port (1, 4, 8, ... to 24) option for scalable high performance applications
- Altera® SOPC Builder software-compliant for easy system integration
- Easy MegaWizard® Plug-In Manager user configuration software
- Many synthesizable options for optimized size and various application needs
- Flexible IP configuration options: MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
- Many external Ethernet interface options for various Altera device families
- MII (10/100 Mb), GMII (10/100/1000 Mb), RGMII and SGMII (10/100/1000 Mb), 1000BASE-X, and TBI (1 Gb)
- MDIO-MDC for PHY device management
- Internal system interfaces
- Altera Avalon®-MM 32 bits for register configuration and monitoring
- Altera Avalon-ST 8 or 32 bits for datapath
- Standard-based statistics counters option
- FIFO or FIFO-less MAC options
- Loop-back option at MII/GMII/RGMII interface
Ease-of-Use
In addition to an FPGA's reprogrammability, ease-of-use is enhanced by the configurability of the solution. The stand-alone MAC, MAC and PCS, or the MAC with PCS and PMA can be chosen with a variety of parallel interfaces including the MII, GMII, RGMII, and TBI, and serial interfaces including SGMII and 1000BASE-X. The parallel interfaces are available in Cyclone®, ArriaTM-GX, and Stratix® FPGA families. The serial interfaces are available in Altera devices with serial transceivers (GX) or in FPGAs with LVDS I/O with dynamic phase alignment (DPA) that can operate up to 1.25 Gbps. The interface FIFO depth and auto-negotiation functions are among several other GUI configurable options.
Figure 1 shows the Triple-Speed Ethernet MegaCore function in an Altera FPGA with a serial transceiver or in a device with LVDS I/O with DPA that can operate up to 1.25 Gbps. The PMA in the embedded serial transceivers of the Altera FPGA is compliant to the IEEE 1000BASE-X PMA specification. The PMA can also be the LVDS I/O DPA operating up to 1.25 Gbps supporting the SGMII interface. In Figure 1, the PMA interoperates with an external physical medium dependent (PMD) device that drives the external copper or optical network. The interconnect between the Altera FPGA and the PMD can be 1000BASE-X or SGMII.
Figure 1. Triple-Speed Ethernet MegaCore Function in an Altera Device
View Full Size
Applications
The applications for the Triple-Speed Ethernet MegaCore function are wide-ranging. Typical applications include:
- Embedded Systems. This MegaCore function has a very low LE count option targeting highly cost-sensitive systems. A design example for high-performance embedded designs, with a TCP/IP stack incorporating the Triple-Speed Ethernet MegaCore function, is available for download
- Telecom. Multiple 1 Gigabit Ethernet ports aggregation to 10 gigabit Ethernet or two gigabit Ethernet links to a 2.5-Gbit link
- Broadcast and Video. Serial digital interface (SDI) or Asynchronous Serial Interface (ASI) video data conversion to gigabit Ethernet for distribution over LAN or metropolitan area network (MAN)
- Protocol Conversion. Conversion from Ethernet to other chip-to-chip protocols such as PCI-Express, the Serial RapidIO®standard, SPI-4.2, and more
Altera provides IP cores and reference designs for several serial protocols, thus providing complete solutions for the above applications and further accelerating your time-to-market.
Robust Solution
Compliance has been tested with several third-party devices and small form-factor pluggable (SFP) modules. The implementation of this MegaCore function on Altera FPGAs, both transceiver-based and non-transceiver-based, has been successfully validated with multiple Ethernet equipment vendors at the UNH-IOL. Additionally, this MegaCore function has been extensively hardware tested on all supported Altera FPGAs.
OpenCore Plus Evaluation
Use the Altera OpenCore Plus evaluation flow to test drive this IP core.
Performance
Typical expected performance and utilization figures for this core are provided in the Triple-Speed Ethernet MegaCore Function User Guide (PDF).
Technical Support
Technical support on this MegaCore function is provided by Altera's mySupport online issue tracking system. You may also search the Altera Knowledge Database for topics related to this function.
Related Documents
|
Literature
> 
