from Altera Corporation
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Feature Rich
- Complete 10/100/1000-Mbps Ethernet intellectual property (IP) with all the necessary IP modules
- 10/100/1000-Mbps media access controller (MAC), physical coding sublayer (PCS) and physical medium attachment (PMA)
- Flexible IP options
- MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
- Many options for various applications and sizes as small as 900 logic elements (small-MAC)
- Standard-based statistics counters supporting SNMP Management Information Base (MIB and MIB-II) and Remote Network Monitoring (RMON)
- Parameterizable FIFO or FIFO-less MAC options
- Optimized multi-port (1, 4, 8, ... to 24) option for scalable high-performance applications
- Many external Ethernet interface options for various Altera® device families
- MII (10/100 Mbps), GMII, RGMII, and SGMII (10/100/1000 Mbps), 1000BASE-X, and TBI (1 Gbps)
- Management data I/O (MDIO) for external PHY device management
Ease of Use
- Complete 10/100/1000-Mbps Ethernet protocol solution available to start your design quickly
- Development boards
- Reference designs
- IP functional simulation models for use in Altera-supported VHDL and Verilog simulators
- Verification test bench and example design
- Ethernet driver software
- Easy IP configuration and generation using Altera MegaWizard® Plug-in Manager GUI software
- Easy system integration with Altera SOPC Builder software
- Quick and easy licensing through OpenCore Plus for your evaluation
Robust Solution
- IEEE 802.3 Ethernet standard compliant
- Successfully validated at University of New Hampshire Interoperability Lab (UNH-IOL)
- Extensively verified in simulation and tested in hardware with third-party test equipment
General Description
As the leading and only provider of gigabit Ethernet in 40-nm FPGA devices, Altera offers the Triple-Speed Ethernet MegaCore® function, allowing you to easily build systems with a 10/100/1000-Mbps Ethernet network connection. Altera Triple-Speed Ethernet consists of a 10/100/1000-Mbps Ethernet MAC and PCS IP. This IP enables Altera FPGAs to interface to an external Ethernet PHY device, which in turn interfaces to the Ethernet network.
The Triple-Speed Ethernet external Ethernet serial interfaces (SGMII and 1000Base-X) are available in all Altera FPGAs and HardCopy® ASICs with serial transceivers, and in Altera devices with LVDS I/Os with dynamic phase alignment (DPA) that can operate up to 1.25 Gbps. The LVDS I/Os enable very scalable multi-port gigabit Ethernet system designs while leaving serial transceivers for higher performance protocols. The parallel interfaces are also available in Cyclone®, Arria® GX, and Stratix® FPGA families and HardCopy ASIC families.
Figure 1 shows the Triple-Speed Ethernet MegaCore function in an Altera device with a serial transceiver or with LVDS I/Os with DPA. The PMA in the embedded serial transceivers is compliant to the IEEE 1000BASE-X PMA standard and compatible with SGMII specification. The PMA can alternatively be an LVDS I/O pin with DPA for SGMII interface.
Figure 1. Triple-Speed Ethernet MegaCore Function in an Altera Device
Protocol Solution
- Detailed documentation on how to use the IP core
- Complete description of Altera device capabilities
- Reference designs for quick and easy design start
- Triple Speed Ethernet Datapath Reference Design (PDF)
- Accelerating Nios® II Networking Applications (PDF)
Performance
Typical expected performance and utilization figures for this core are provided in the Triple-Speed Ethernet MegaCore Function User Guide (PDF).
Technical Support
For technical support on the Triple-Speed Ethernet MegaCore Function, please visit the Triple-Speed Ethernet MegaCore Support Center. Additional support for MegaCore functions is available in the Altera mySupport online issue tracking system. You may also search the Altera Knowledge Database for topics related to this function.
