As the leading provider of 1 Gbps Ethernet (GbE) for FPGA and HardCopy® ASIC devices, Altera offers the Triple-Speed Ethernet MegaCore® function, allowing you to easily build systems with a 10/100/1000 Mbps Ethernet network connection. Altera's Triple-Speed Ethernet consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) intellectual property (IP). This IP function enables Altera® FPGAs to interface to an external Ethernet PHY device, which, in turn, interfaces to the Ethernet network.
The Triple-Speed Ethernet's external Ethernet serial interfaces (SGMII and 1000Base-X) are available in all Altera FPGAs and HardCopy ASICs with serial transceivers. You can also find these interfaces in Altera devices with LVDS I/Os with dynamic phase alignment (DPA) that can operate up to 1.25 Gbps. The LVDS I/Os enable very scalable multi-port GbE system designs while leaving serial transceivers for higher performance protocols. The parallel interfaces are also available in Cyclone®, Arria® GX, and Stratix® FPGA families and HardCopy ASIC families.
Figure 1 shows the Triple-Speed Ethernet MegaCore function in an Altera device with a serial transceiver or with LVDS I/Os with DPA. The physical medium attachment (PMA) in the embedded serial transceivers is compliant to the IEEE 1000BASE-X PMA standard and compatible with SGMII specification. The PMA can alternatively be an LVDS I/O pin with DPA for SGMII interface.
Figure 1. Triple-Speed Ethernet MegaCore Function in an Altera Device
- Complete 10/100/1000 Mbps Ethernet IP with all the necessary IP modules
- 10/100/1000 Mbps MAC, PCS, and PMA
- Flexible IP options
- MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
- Many options for various applications and sizes as small as 900 logic elements (small-MAC)
- Standard-based statistics counters supporting simple network management protocol (SNMP) Management Information Base (MIB and MIB-II) and Remote Network Monitoring (RMON)
- Parameterizable FIFO or FIFO-less MAC options
- IEEE 1588 v2 high accuracy and high precision time stamping option in hardware IP
- 1-step and 2-step time sync
- Supports IEEE 1588 v2 PTP packet encapsulation in IPv4, IPv6 and Ethernet
- Real time of day clock generator (ToD) IP in design example
- Many external Ethernet interface options for various Altera device families
- MII (10/100 Mbps), GMII, RGMII, and SGMII (10/100/1000 Mbps), 1000BASE-X, and TBI (1 Gbps)
- Management data I/O (MDIO) for external PHY device management
Easy to Use
- Complete 10/100/1000 Mbps Ethernet protocol solution available to start your design quickly
- Development boards
- Reference designs
- RTL and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
- Verification testbench and example design
- Ethernet driver software
- Easy IP configuration and generation using Altera MegaWizardTM Plug-In Manager parameter editor
- Easy system integration with Altera SOPC Builder and Qsys software
- Quick and easy licensing through OpenCore Plus for your evaluation
- Detailed documentation on how to use the IP core
- Complete description of Altera device capabilities
- Reference designs for quick and easy design start
Resource Utilization and Performance
Estimated resource utilization and performance figures for this IP core are provided in the Triple-Speed Ethernet MegaCore Function User Guide (PDF).
For technical support on the Triple-Speed Ethernet MegaCore Function, please visit the Triple-Speed Ethernet IP Core Resource Center. Additional support for MegaCore functions is available in the Altera mySupport online issue tracking system. You may also search the Knowledge Base for topics related to this function.