Gigabit Ethernet MAC
Features
The Gigabit Ethernet MAC megafunction includes the following features:
- Nios® embedded processor interface
- 1000 Base-T, full duplex
- 100 Base-TX, full duplex
- Transmit buffer: double buffer, 2000 bytes
- Receive buffer: ring buffer, 4000 bytes
- Filter: MAC ID, MAC IP, MAC control frame (MCF)
- IFI_PHY_MANAGER included
- Adapted for UCOSII Lightweight IP TCP/IP stack
- Adapted for standalone Lightweight IP TCP/IP stack
- Adapted for emBetter TCP/IP stack
Block Diagram
Figure 1 shows the block diagram of the megafunction.
Figure 1. Gigabit Ethernet MAC Block Diagram
 View full detail (191 KB)
Description
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Small but efficient Gigabit Ethernet MAC
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Easily integrated into Nios II systems using SOPC Builder
-
Avalon® interface for Nios II processor
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Independent clock domains for Nios II and GMAC II
-
Royalty free
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Ethernet and Gigabit Ethernet PHY module available
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Software drivers shipped with IP
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Verified on Nios II development board
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Evaluation version available
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization |
| Target Device |
Utilization Logic
Elements (LEs) (1)
|
M4K Memory blocks |
I/O Pins |
| Cyclone™ FPGA |
1100 |
16 |
27 |
| Cyclone II FPGA |
1100 |
16 |
27 |
| Stratix® FPGA |
1100 |
16 |
27 |
| Stratix II FPGA |
1100 |
16 |
27 |
Note:
- The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.
Contact Information
For additional information, contact:
Ingenieurbüro Für IC-Technologie
Kleiner Weg 3
97877 Wertheim
GERMANY
Tel: +49/9342/96080
Fax: +49/9342/5381
Email: ifi@ifi-pld.de
URL: www.ifi-pld.de
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