High Performance Gigabit Ethernet MAC
Features
The High Performance Gigabit Ethernet MAC includes the following features:
- Up to 114 Mbytes of UDP data
- 1000 Base-T, full duplex
- 100 Base-TX, full duplex
- Transmit buffer: double buffer, 2000 bytes, checksum advance logic
- Receive buffer: ring buffer, 4000 bytes
- Filter: MAC ID, MAC IP
- Integrated DMA controller: pipelined, generates checksum on the fly, alignment aware
- IFI_PHY_MANAGER included
- Nios® II embedded processor interface
Block Diagram
Figure 1 shows the block diagram of the megafunction.
Figure 1. High Performance Gigabit Ethernet MAC Block Diagram
 View full detail (192 KB)
Description
- Easily integrated into Nios II systems using SOPC Builder
- Avalon® interface for Nios II processor
- Independent clock domains for Nios II and GMAC II
- Royalty free
- Ethernet and Gigabit Ethernet PHY module available
- Verified on Nios II development board
- Evaluation version available
- Reference software included
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Devices |
Utilization Logic
Elements (LEs) (1)
|
M4K Memory Blocks |
I/O Pins |
| Cyclone™ FPGA |
2400 |
17 |
27 |
| Cyclone II FPGA |
2650 |
17 |
27 |
| Stratix® FPGA |
2400 |
17 |
27 |
| Stratix II FPGA |
2100 |
17 |
27 |
Note:
- The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.
Contact Information
For additional information, contact at:
Ingenieurbüro Für IC-Technologie
Kleiner Weg 3
97877 Wertheim
GERMANY
Tel: +49/9342/96080
Fax: +49/9342/5381
Email: ifi@ifi-pld.de
URL: www.ifi-pld.de
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