10/100/1000 Mbps Ethernet MAC

from MorethanIP

Features

• IEEE 802.3 specification with preamble/start-of-frame delimiter (SFD) generation, frame padding generation, and cyclic redundancy code (CRC) generation and checking on respective transmit and receive is fully implemented
• Configuration dynamically supports 10-Mbps, 100-Mbps, or 1-Gbps operation
• 10- or 100-Mbps operation uses full- or half-duplex operation support (selectable via a core configuration option)
• Interface connects seamlessly to commercial Gigabit Ethernet physical layer (PHY) device via a 8-bit gigabit medium independent interface (GMII) operating at 125 MHz
• Interface connects seamlessly to commercial Fast Ethernet PHY device via a 4-bit medium independent interface (MII) operating at 25 MHz
• Integrated 1000Base-X physical coding sub-layer (PCS) and physical medium attachment (PMA) (optional) when implemented in Altera^® Stratix^™ GX devices with 8b/10b coding decoding and frame encapsulation
• Serial 1.25-Gbps medium dependent interface (MDI) (optional) implemented with Altera Stratix GX-embedded serializer/deserializer (SERDES)
• First-in first-out (FIFO) interface to user application
• CRC-32 checking at full speed that uses a multi-stage CRC calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application
• CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
• Fully automated pause frame (802.3 Annex 31A) generation and termination implemented upon full duplex mode operation, providing flow control without user application intervention
• Pause quanta forms pause frames during full duplex mode operation; dynamically programmable
• Pause frame generation controllable by user application offering flexible traffic flow control
• Received pause frames forwarding (optional) to the user application during full duplex mode operating
• Flow-control mechanism standard in full-duplex operation mode
• Half-duplex mode provides full collision support, including jamming, backoff, and automatic retransmission
• VLAN tagged frames support (according to IEEE 802.1Q) support
• Programmable media access control (MAC) address: insertion on transmit, and discarding of frames with mismatching destination address on receive (except broadcast and pause frames)
• Programmable promiscuous mode support to omit MAC destination address-checking on receive
• Multicast address filtering-on-receive based on 64-entries hash table, reducing higher layer processing load
• Programmable frame maximum length providing support for any standard or proprietary frame length (e.g., 9-Kbyte jumbo frames)
• Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames providing for basic and mandatory management information database (MIB) package enabling implementation in simple network management protocol (SNMP) management environments
• Simple handshake user application FIFO interface with fully programmable depth and threshold levels, ensuring data rates of 1 Gbps with full, back-to-back frame transfer support
• Status word available separately for each received frame on the user interface, providing information such as frame length, frame type, and VLAN tag and error information
• CPLD or ASIC implementation, and ASSP (application-specific standard product) implementation
• Design kit with extensive Ethernet frame generators and checking models, enabling fully automated design verification and testing for standard compliance and error behavior, enabling for fast turn-around design cycles

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. 10/100/1000 Mbps Ethernet MAC Block Diagram

Description

The programmable 10/100/100 Ethernet MAC uses a single intellectual property (IP) core to provide a solution for Ethernet applications (switching, line card, or network interface (NIC)) operating at 10, 100, or 1,000 Mbps. The 10/100/1000 Ethernet MAC core operates in full duplex mode, and supports termination and generation for transparent (switching) and full Ethernet frame (NIC or line card) applications.

The core connects seamlessly to any industry-standard gigabit Ethernet PHY device via a medium independent interface (MII) for 10- and 100-Mbps applications, or gigabit medium independent interface (GMII) for 1,000-Mbps applications. It also connects to a user application via a system-on-a-chip (SOC) interface, and provides seamless connectivity to any MorethanIP cores such as Flexbus, packet over SONET-physical layer (POS-PHY); PCI interfaces; or any third-party core which implements an interface compatible with the Altera Atlantic^™ interface specification.

Optionally, the core implements an integrated 1000 Base-X PCS and physical media attachment (PMA) for gigabit-only operation when implemented in Altera Stratix GX devices. Using a Stratix GX embedded SERDES reduces board complexity and system cost. Designers can also deliver the core through generic synthesizable hardware description language (HDL) code (for use in Altera CPLD or ASIC technologies), as a CPLD netlist, which provides a lower cost solution.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

Register transfer level (RTL) synthesizable VHDL/Verilog source code or encrypted netlist

• Configurable VHDL and Verilog verification testbenches
• Scripts for Mentor Graphics^® LeonardoSpectrum^™ synthesis tool
• Implementation script for the Quartus^® II version 2.2 software
• Detailed user and reference guides

Contact Information

For additional information, contact:

MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld Germany

Tel: +49 81-31-333-9390 (Germany) or +1 408-273-4567 (USA)
Fax: +49 81-31-333-9391 (Germany) or +1 408-273-4667 (USA)
E-mail: info@morethanip.com
Internet: http://www.morethanip.com