10/100/1000 Ethernet MAC with Protocol Acceleration

from MorethanIP

Features

• Implements the full 802.3 specification with preamble / SFD generation, frame padding generation, cyclic redundancy code (CRC) generation and checking on transmit and receive respectively
• Supports dynamically programmable 10Mbps, 100Mbps, and 1000Mbps operation
• Supports full-duplex or half-duplex operation selectable via a Core configuration option
• Seamless interface to commercial Fast Ethernet PHY device via a 4-Bit Medium Independent Interface (MII) operating at 25MHz
• 32-Bit Avalon™ Streaming Bus System On a Chip (SOC) interfaces allowing for efficient direct memory access (DMA) transactions
• 32-Bit Avalon System Interface with separate slave ports for data and control
• Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames)
• Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames providing for IEEE 802.3 basic and mandatory Management Information Database (MIB) package as well as Ethernet MIB (RFC 2665) and Remote Network Monitoring (RFC 2819) enabling implementation in simple network management protocol (SNMP) management environments
• Includes data path first-in first-outs (FIFOs) with fully programmable depth and threshold levels ensuring data rates of 1Gbps with full back-to-back frame transfer support
• The MAC is fully integrated in Altera's SOPC Builder with supporting files for easy system configuration and generation
• C Software drivers and example applications
• Protocol Acceleration Functions
• Operates on transmission control protocol/Internet protocol (TCP/IP) and user datagram protocol/Internet protocol (UDP/IP) and Internet control message protocol/Internet protocol (ICMP/IP) data or IP header only
• Support for IP and TCP, UDP, ICMP data for checksum generation and checking

Block Diagram

Figure 1. 10/100/1000 MAC-NET Block Diagram

Description

The MAC-NET Core implements a 10/100/1000 Ethernet MAC combined with network acceleration functions, which are designed to accelerate the processing of various common networking protocols such as IP, TCP, UDP and ICMP.

The Core implements a triple speed 10/100/1000Mbps Ethernet MAC compliant with the IEEE802.3-2002 standard. The MAC layer provides compatibility with Full Duplex Gigabit Ethernet LANs as well as Half- or Full-Duplex 10/100Mbps Ethernet and Fast Ethernet LANs.

The MAC operation is fully programmable and can be used in Network Interface Card (NIC), bridging or switching applications. For Simple Network Management Protocol (SNMP) the Controller implements IEEE Statistics, Management Information Base (MIB, MIB-II) according to IETF RFC2665 and Remote Network Monitoring (RMON) according to IETF RFC 2819. All registers are accessible via a 32-Bit parallel interface.

The MAC-NET Core implements a hardware acceleration block to optimize the performance of network controllers providing IP and TCP, UDP, ICMP protocol services. The acceleration block performs critical functions, which are typically implemented with large software overhead allowing high performance networking applications and at the same time reducing processor load.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

• Detailed user's guide and reference guide
• Register Transfer Level (RTL) synthesizable VHDL / Verilog source code or encrypted netlist
• Configurable VHDL / Verilog verification test-benches
• Scripts for Leonardo Spectrum synthesis tool
• SOPC Builder supporting files (System ptf and Software SDK)
• Implementation script for Quartus^® II software
• C Software driver examples, test examples, and networking drivers

Contact Information

For additional information, contact MorethanIP:

MorethanIP
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Karlsfeld Germany

Tel: +49 81-31-333-9390 
Fax: +49 81-31-333-9391 
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