10/100 Ethernet MAC

from MorethanIP

Features

• Implements the full 802.3 specification with preamble/start frame delimiter (SFD) generation, frame padding generation, cyclic redundancy code (CRC) generation, and checking on transmit and receive respectively
• Supports 10-Mbps and 100-Mbps operation
• Supports full-duplex or half-duplex operation selectable via a core configuration option
• Seamless interface to commercial fast Ethernet PHY device via a 4-bit Medium Independent Interface (MII) operating at 25 MHz
• 32-Bit Avalon™ streaming bus system-on-a-chip (SOC) interfaces allow for efficient direct memory access (DMA) transactions
• 32-Bit Avalon System Interface with separate slave ports for data and control
• CRC-32 checking at full speed with optional forwarding of the frame check sequence (FCS) field to the user application
• CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
• Programmable frame maximum length providing support for any standard or proprietary frame length (e.g., 9-Kbyte jumbo frames)
• Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames providing for IEEE 802.3 basic and mandatory Management Information Database (MIB) package as well as Ethernet MIB (RFC 2665) and Remote Network Monitoring (RFC 2819) enabling implementation in simple network management protocol (SNMP) environments
• Includes data path first-in first-out (FIFO) interfaces with fully programmable depth and threshold levels ensuring data rates of 1Gbps with full back-to-back frame transfer support
• MDIO Master interface for PHY device configuration and management with two programmable MDIO base addresses
• Media access controller (MAC) fully integrated in Altera's SOPC Builder with supporting files for easy system configuration and generation
• C Software drivers, example applications, and driver for TCP/IP networking libraries

Block Diagram

Figure 1 shows MorethanIP's 10/100 Ethernet MAC Core.

Figure 1. 10/100 Ethernet Media Access Controller Core

Description

The programmable 10/100 Ethernet MAC from MorethanIP provides, with a single intellectual property (IP) core solution, a solution for Ethernet applications (line card, network interface card (NIC), or switching) operating at 10 or 100 Mbps. The 10/100 MAC core can operate in half- or full-duplex mode, supports transparent (for switching applications) and full Ethernet frame termination/generation (for NIC or line cards applications).

The core can seamlessly connect to any industry standard PHY with Media Independent Interface (MII) and to a user application via the Avalon SOC interface available, for example, with Nios^® embedded processor environments. Optionally, the core is also available with a generic FIFO interface (Atlantic™ interface compatible).

The core is optionally delivered in generic synthesizable hardware description language (HDL) code, or as a FPGA netlist. In addition, MorethanIP also provides a programmable 10/100/1000 Ethernet MAC core.

The MAC comes integrated in Altera's SOPC Builder for easy system configuration and generation and drivers are provided to use the MAC with networking libraries.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

• Detailed user's guide and reference guide
• Register Transfer Level (RTL) synthesizable VHDL/Verilog source code or encrypted
• Configurable VHDL/Verilog verification test-benches
• Scripts for LeonardoSpectrum™ synthesis tool
• SOPC Builder supporting files (System peripheral template file (ptf) and Software SDK)
• Implementation script for Quartus^® II
• C software driver examples, test examples, and networking drivers

Contact Information

For additional information, contact MorethanIP:

MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld, Germany

Tel: +49 81-31-333-9390 
Fax: +49 81-31-333-9391 
Email: info@morethanip.com
URL: http://www.morethanip.com