from MorethanIP
      |
Features
- IEEE 802.3 specification is fully implemented with preamble/start-of-frame delimiter (SFD) generation, frame padding generation, and cyclic redundancy code (CRC) generation and checking on respective transmit and receive
- Seamless interface to commercial Gigabit 10/100/1000 physical layer (PHY) device via 1.25-Gbps serial Gigabit medium independent interface (SGMII).
- Implements low pin count SGMII to commercial Ethernet PHY of small form-factor pluggable (SFP) modules
- Supports 10/100 Mbps operation, full duplex or half duplex operation selectable via core configuration option
- Optional physical medium attachment (PMA) serializer/deserializer (SERDES) when implemented in Altera® Stratix® GX
- Simple FIFO interface to user application compatible with Altera Atlantic specification
Block Diagram
Figure 1 shows MorethanIP's 10/100/1000 Ethernet media access controller (MAC) core with an SGMII.
Figure 1. 10/100/1000 Ethernet MAC Core With SGMII
Click for full detail (105 KB)
Note:
- MDIO = management data input/output
- 8B/10B = 8 bit/10 bit
Description
The programmable 10/100/1000 Ethernet MAC from MorethanIP provides, with a single intellectual property (IP) core, a solution for Ethernet applications (line card, NIC card, or switching) operating at 10/100 or 1000 Mbps (Gigabit Ethernet). The 10/100/1000 Ethernet MAC core can operate in half (10/100-Mbps operation only) or full duplex mode, supports transparent (for switching applications) and full Ethernet frame termination/generation (for NIC or line card applications).
The core implements a low pin count SGMI which integrates a 1000 Base-X compliant with Clause 36 of the IEEE 802.3 standard and implements 8B/10B coding, link synchronization, and frame encapsulation generation/termination. The core also supports auto-negotiation (Clause 37 of the IEEE 802.3 standard), which is used to automatically, or under user application software control, exchange ability information between the core and the remote end of the link and to configure the core to best use the advertised features of the remote node.
The core can seamlessly connect to any industry standard 10/100/1000 Ethernet SERDES device via an SGMII and to a user application via a system-on-a-chip (SOC) interface, which provides seamless connectivity to any MorethanIP core with a packet over SONET (POS)-PHY interface, such as Flexbus.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | |||||
| Target Device | Speed Grade |
Utilization Logic |
Performance (fMAX) |
Parameter Setting | |
|---|---|---|---|---|---|
| Stratix | -7 | 4,900 | 137 MHz | 125 MHz | |
| Stratix GX | -7 | 4,900 | 140 MHz | 125 MHz | |
| Cyclone™ | -8 | 5,000 | 127MHz | 125 MHz | |
| Stratix II | -5 | 4,400 | 152 MHz | 125 MHz | |
| Cyclone II | -8 | 5,000 | 132 MHz | 125 MHz | |
Note:
- The Quartus® II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.
Deliverables
- Detailed user's guide and reference guide
- Register transfer level (RTL) synthesizable VHDL/Verilog source code or encrypted code
- Configurable VHDL/Verilog verification test-benches
- Implementation script for Quartus II
Contact Information
For additional information, contact MorethanIP:
MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld Germany
Tel: +49 81-31-333-9390
Fax: +49 81-31-333-9391
Email: info@morethanip.com
URL: http://www.morethanip.com
