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High Speed I2C Bus Controller

Home > Products > Intellectual Property > Interfaces & Peripherals > I2C > High Speed I2C Bus Controller

from CAST, Inc.

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AMPP Approved
OpenCore Support



Features

  • Transfers information between devices connected to the bus using two wires:
    • Serial clock line (SCL)
    • Serial data line (SDA)
  • Performs serial transmission up to 100 kHz in four modes:
    • Master transmitter mode: Serial data output through SDA while SCL outputs the serial clock.
    • Master receiver mode: Serial data is received via SDA while SCL outputs the serial clock.
    • Slave receiver mode: Serial data and the serial clock are received through SDA and SCL.
    • Slave transmitter mode: Serial data is transmitted via SDA while the serial clock is input through SCL.

Block Diagram

Figure 1 shows the block diagram for the I2C Bus Controller megafunction.

Figure 1. Block Diagram

Figure 1. Block Diagram

Description

The I2C Bus Controller megafunction provides a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic handles byte transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.

The I2C function is a microcode-free design developed for reuse in application-specific integrated circuit (ASIC) and programmable logic device (PLD) implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
Logic Elements (1) Memory
Cyclone™ 1C3 -6 387 - 200 MHz Contact CAST
Stratix® 1S10 -5 385 - 205 MHz Contact CAST
Stratix II 2S3 -6 369 - 296 MHz Contact CAST

Note:

  1. The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.

Deliverables

  • Encrypted Licenses
    • Post-synthesis Altera hardware description language (AHDL) or electronic data interchange format (EDIF)
    • Assignment and configuration
    • Symbol file
    • Include file
    • Graphic design file with sample design
    • Vectors for testing the functionality of the megafunction
  • HDL Source Licenses
    • VHDL or Verilog register transfer level (RTL) source code
    • Testbench
    • Example testbench wrapper for post-route simulation
    • Vectors for testbench
    • Simulation script
    • Synthesis script
    • Expected results for testbench

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: info@cast-inc.com
URL: http://www.cast-inc.com

Note: The I2C megafunction is licensed from Evatronix S.A.

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