High-Performance Memory Controller II SDRAM MegaCore Function

from Altera

The High-Performance Memory Controller II SDRAM MegaCore^® function handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM. The function initializes the memory devices, manages SDRAM banks, and translates read and write requests from the local interface into all the necessary SDRAM command signals.

The High-Performance Memory Controller II core is a drop-in replacement for the existing SDRAM controller, with many new enhanced features. New features include advanced bank management and a flexible system interface, both of which improve core efficiency.

Block Diagram

Whether you use the IP Toolbench in SOPC Builder or Quartus^® II software, it generates an example design, an example driver, and the DDR1, DDR2, and DDR3 SDRAM controller, and instantiates a phase-locked loop (PLL). This fully functional design example can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller, and checks the read data to produce the pass/fail and test complete signals.

Included in the IP Base Suite—FREE with Quartus II Subscription Edition software

Features

• Support for industry-standard DDR, DDR2, and DDR3 SDRAM devices and modules
  • Includes support for registered DIMMs
  • Supports efficient bank interleaving
• Look-ahead bank management
  • Issue activate and precharge commands early
    • Use auto-precharge when possible
    • In-order read/writes (no re-ordering)
  • Bank management architecture, which minimizes latency
  • Read/write accesses with auto-precharge
    • Automatic cancellation of auto-precharge on page hits
• Avalon^® Memory-Mapped interface
  • Adaptor for native interface
  • Avalon slave interface for access to CSR
• Burst size adaptation for efficient DRAM accesses
  • Built-in burst adapter
  • Combines short local transactions into memory bursts
  • Split long local transactions into memory bursts
• Integrated low-latency half-rate system interface
  • Support an optional half-system interface speed
  • Maintain the controller in the faster clock domain to reduce latency
• Flexible, robust design
  • 1, 2, 4, or 8 chip-select signals
  • Configurable data width including data strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Stratix^® series FPGAs)
  • Automatic or user-controlled refresh
  • Data mask signals for partial write operations
• Quick and easy implementation
  • IP Toolbench-generated constraint script
  • Top-level example design shipped as a deliverable with the intellectual property (IP) MegaCore function
  • IP functional simulation models used in Altera^® supported VHDL and Verilog HDL simulators
  • Available in clear-text for use with custom controller
• SOPC Builder ready to enable system-level design

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this IP core.

Performance

• Supports up to 533-MHz memory speed at half rate (267-MHz controller clock)
• 5-cycle controller latency

Typical expected performance and utilization figures for this MegaCore function are provided in the High-Performance Memory Controller II SDRAM Controller Compiler User Guide.

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

Related Documents

For more information on the DDR and DDR2 SDRAM Controller MegaCore functions, refer to the following documents:

• Users Guide High Performance Memory Controller II 
• MegaCore IP Library Release Notes and Errata (PDF)