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Home > Products > Intellectual Property > Interfaces & Peripherals > Memory Controllers > QDRII SRAM Controller MegaCore Function Print This Page Subscribe to Email QDRII SRAM Controller MegaCore Function from Altera Corporation Included in theIP Base Suite—FREE with Quartus II Subscription Features Support for QDRII and QDRII+ SRAMs Support for burst of two and four memory type Support for 8-bit, 18-bit, and 36-bit QDRII SRAM interfaces Flexible and robust design Support for two-times and four-times data width on the local side (four-times for burst of four only) Automatic concatenation of consecutive reads and writes (narrow local bus width mode only) Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Easy-to-use IP Toolbench interface and example design   Support for OpenCore Plus evaluation General Description The QDRII SRAM Controller MegaCore®function provides an easy-to-use interface to QDRII SRAM and QDRII+ SRAM modules. The QDRII SRAM controller ensures that the placement and timing are in line with QDRII specifications. The QDRII SRAM controller’s local interface is compatible with the Altera®Avalon®Memory-Mapped interface, for easy integration into SOPC builder. The QDRII SRAM Controller MegaCore functionis optimized for Altera Stratix®series FPGAs. The advanced features available in these devices allow you to interface directly to QDRII SRAM devices. The IP Toolbench-generated example design instantiates a phase-locked loop (PLL), an optional DLL (for Stratix II FPGAs only), an example driver, and your QDRII SRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. You can replace the QDRII SRAM controller encrypted control logic in the example design with your own custom logic, which allows you to use the Altera clear-text resynchronization and pipeline logic and datapath with your own control logic. IP Evaluation Use the AlteraOpenCore Plus Evaluationflow to test drive this MegaCore function. Performance Typical expected performance and utilization figures for this MegaCore function are provided in theQDRII SRAM Controller MegaCore Function User Guide(PDF). I-Tested Altera awards theI-Tested certificationto MegaCore functions or Altera Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols. For more information, see MegaCore Verification in theQDRII SRAM Controller MegaCore Function User Guide(PDF). Technical Support For technical support on this MegaCore function, please visit theAltera mySupportonline issue tracking system. You may also search for related topics on this function in theAltera Knowledge Database. Related Documents QDRII SRAM Controller MegaCore Function User Guide(PDF) MegaCore IP Library Release Notes and Errata(PDF) AN326: Interfacing QDRII SRAM With Stratix II, Stratix, and Stratix GX Devices(PDF) Rate This Page

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