RLDRAM II Controller MegaCore Function

from Altera Corporation

Included in the IP Base Suite—FREE with Quartus^® II Design Software Subscription

Features

• Support for industry-standard RLDRAM II components
  • Common I/O (CIO) and separate I/O (SIO) device support
• Flexible and robust design
  • Non-multiplexed addressing
  • Datapath generation
  • Data strobe signal (DQS) and non-DQS capture modes
  • Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
  • Easy-to-use IP Toolbench interface and automatic constraint generation

General Description

The RLDRAM II Controller MegaCore^® function handles the complex aspects of using RLDRAM II—initializing the memory devices and translating read and write requests from the local interface into all the necessary RLDRAM II command signals.

The RLDRAM II controller is optimized for Altera^® Stratix^® IV, Stratix III, Stratix II, Stratix GX, and HardCopy^® II devices. The advanced features available in these devices allow you to interface directly to RLDRAM II devices.

IP Toolbench generates the following items:

• A testbench, which instantiates the example design
• A synthesizable example design that instantiates the following modules:
  • RLDRAM II controller:
    • Encrypted control logic, which takes transaction requests from the local interface and issues writes, reads, and refreshes to the memory interface
    • A clear-text datapath
  • Example driver—generates write, read, and refresh requests and outputs a pass/fail signal to indicate that the tests are passing or failing
  • System phase-locked loop (PLL)—generates the RLDRAM II controller clocks
  • Delay-locked loop (DLL)—instantiated in DQS mode and generates the DQS delay control signal for the dedicated DQS delay circuitry
  • Optional feedback clock PLL—instantiated in non-DQS mode and generates a capture clock for the datapath read capture and logic path

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this MegaCore function.

Performance

Typical expected performance and utilization figures for this MegaCore function are provided in the RLDRAM II Controller MegaCore Function User Guide (PDF).

I-Tested

Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPP^SM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

For more information, see MegaCore Verification in the RLDRAM II Controller MegaCore Function User Guide (PDF).

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

Related Documents

For more information on the RLDRAM II Controller MegaCore function, refer to the following documents:

• RLDRAM II Controller MegaCore Function User Guide (PDF)
• MegaCore IP Library Release Notes and Errata (PDF)
• AN 325: Interfacing RLDRAM II with Stratix II, Stratix, and Stratix GX Devices (PDF)