DMA Controller Features
- General-purpose direct-memory access (DMA) controller
- Up to 16 DMA channels
- Supports both synchronous and asynchronous DMA transfers
- Designed for peripheral component interconnect (PCI) and other central processing unit (CPU) bus systems
DMA Controller Block Diagram
Figure 1 shows the block diagram for the DMA controller megafunction.
|Figure 1. DMA Controller Block Diagram|
DMA Controller Description
The DMA controller megafunction is designed for data transfer in different system environments. Two module types—type 0 and type 1—are provided, and the user can choose the number of each module type. Type 0 modules are designed to transfer data residing on the same bus, and Type 1 modules are designed to transfer data between two different buses. Each module can support up to 4 DMA channels; the megafunction supports up to 16 total DMA channels.
Each DMA channel can be programmed for various features, such as transfer size, synchronized and unsynchronized transfer control, transfer priority, interrupt generation, memory and I/O address space, and address change direction. This megafunction is designed to work with 32-bit and 64-bit bus systems, including the PCI bus, PowerPC bus, and other CPU host buses. It can also be integrated with other megafunctions to form a complete functional block.
This megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
|Table 1. Typical Device Utilization for the Megafunction|
|Logic Cells||EABs (1)|
- EABs = Embedded array blocks
For additional information, you can contact Eureka Technology, Inc. at:Eureka Technology, Inc.
4962 El Camino Real
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805