from Eureka Technology Inc.
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Features
- Supports up to 32 Gbytes of NAND flash devices with 8 banks
- Each bank contains up to 5 NAND flash connected in parallel for 32-bit data and 8-bit ECC
- Simple user interface for easy on-chip integration
- Programmable support for large block and small block NAND flash devices
- Large flash memory space can be accessed using data and index register methods
- Programmable access timing
- User has full access to spare data in NAND flash device
- No wait state on reading new page by using write-triggered read
- Supports boot ROM application by automatic page open upon reset
- Supports two-plane page program and erase for doubling system bandwidth
- Optional ECC protection on a per-word or per-page basis
- Word-wise ECC adds 8-bits of ECC to each 32-bit word data for single-bit error correction and double bit error detection
- Page-wise ECC provides single-bit error correction and double bit error detection of each page of data
- Error logging with ECC correction and detection
- Interrupt generation based on ECC error
- Options to provide PCI, AHB, AXI, Wishbone, SH4 and Avalon® bus interfaces
Block Diagram
Figure 1 shows the block diagram for the NAND Flash Controller megafunction.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | |||
| Device | Speed Grade | Utilization | |
|---|---|---|---|
| Logic Cells | EABs (1) | ||
| Cyclone® III FPGA | -6 | 1419 LEs | 0 |
| Stratix® III FGPA | -3 | 1008 ALM | - |
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
