Pipeline SDRAM Controller
Features
- Designed with synthesizable hardware description language (HDL) for programmable logic device (PLD) and ASIC synthesis
- Supports both discrete SDRAM chips and PC100/133 SDRAM dual in-line memory module (DIMM)
- Supports register mode and non-register mode SDRAM DIMM
- Supports industrial standard SDRAM from 64 Mbit to 256 Mbit device sizes
- Pipeline access allows continuous data transfer without wasted cycle
- Supports column-only access on page hits
- Programmable memory size: 4,8,16, and 32 bits per SDRAM
- Programmable word size: 16, 32, and 64 bits
- Supports all burst lengths: 1, 2, 4, 8, and full page
- Zero wait state burst data transfer
- Programmable SDRAM access timing parameters
- Automatic refresh generation with programmable refresh intervals
- Programmable memory configuration registers
- Supports external data buffer between the user device and SDRAM data bus by providing a transmit/receive signal
Block Diagram
Figure 1 shows the block diagram for the pipeline SDRAM controller megafunction.
| Figure 1. Block Diagram |
 |
Description
The pipeline SDRAM controller is a high-performance SDRAM controller designed for transferring data to and from any industry standard SDRAM or PC100/133 SDRAM DIMM at the highest possible data rate. It interfaces between a multiple SDRAM memory subsystem and a user interface. It performs SDRAM read and write accesses based on user requests.
The pipeline feature allows the user to specify the next access address while the current data transfer is in progress. It also allows column-only access for both read and write. The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs.
This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Device Utilization Example
Table 1 shows the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX
APEX
ACEX |
|
1,000 |
0 |
66 MHz |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Eureka Technology, Inc. at: Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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