Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
          Peripherals
          PCI
          PCI Express
          Memory Controllers
          USB
          PCMCIA
          Ethernet
          I2C
          CAN
          PowerPC Bus
          HyperTransport
          RapidIO
          SerialLite
          Additional Functions
          Consortiums
          Literature
   DSP
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

DDR SDRAM Controller

from Northwest Logic, Inc.

View Literature



AMPP Approved
OpenCore Support



Features

  • High-performance access logic with read and write queuing enables the highest possible throughput for all burst length (BL) settings: BL2, BL4, BL8
  • Pipelined design enables high clock rates with minimal routing constraints 
  • Bank management logic monitors status of each SDRAM bank (up to 16 banks monitored)—banks only opened or closed when necessary, minimizing access delays
  • Datapath logic specifically optimized for each Altera® FPGA family (Stratix® II, Stratix II GX, Cyclone® II)
  • Run-time configurable timing parameters: tCL, tRAS, tRC, tRFC, tRCD, tRP, tMRD, tRRD, tXSNR, tREFC, and tWR 
  • Supports auto-precharge option enabling low random access latencies
  • Supports SDRAM self-refresh and power-down modes
  • Run-time configurable memory settings (i.e., row bits, column bits, bank bits)
  • Automatically generates initialization and refresh sequences
  • Supports all standard SDRAM devices and dual in-line memory modules (DIMMs)
  • Available with multi-port, front-end module option—provides an 8-port interface to the controller with command reordering, extended burst size, and memory test functions
  • Optional error correction coding (ECC) and read-modify-write with multi-burst, add-on modules available
  • Source code license available in VHDL or Verilog HDL 
  • Fast response time, expert technical support provided by experienced Northwest Logic intellectual property (IP) designers

Block Diagram

Figure 1 shows the block diagram for the DDR SDRAM controller.

Figure 1 shows the block diagram for the double data rate (DDR) SDRAM Controller

View Full Size

Description

Northwest Logic's DDR SDRAM controller provides a high-performance interface to DDR SDRAM devices. The controller is optimized to achieve high-performance, high-frequency operation with minimal constraints.

Bank management techniques are used to monitor the status of each DDR SDRAM bank. Banks are opened or closed only when necessary, minimizing access delays. Up to 16 banks can be managed simultaneously. Access cascading is also supported, enabling read or write requests to be chained together. These bank management techniques result in zero delay between requests, enabling up to 100 percent memory throughput for sequential accesses (not including refresh).

A simple local interface is provided for easy integration with other device logic such as microcontroller buses and FIFO interfaces. The controller is provided with run-time programmable configuration ports for all timing parameters (CAS Latency, tRC, tRAS, tRCD, tRP, tMRD, tRRD, tXSNR, tREFC, tRFC, and tWR), as well as memory configuration settings. This ensures compatibility with virtually any DDR SDRAM configuration.

The DDR SDRAM controller core is available with an optional multi-port, front-end module—providing eight user ports to the controller. The module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port, front-end module can perform command reordering to achieve optimal SDRAM bandwidth. The multi-port, front-end module also includes an extended burst interface and a built-in memory test module.

The DDR SDRAM controller core is also available with optional ECC and read-modify-write modules.

Device Utilization Example

Table 1 lists the typical device utilization results for the DDR SDRAM controller core.

Table 1. Typical Device Utilization for Northwest Logic DDR SDRAM Core
Supported Altera® Devices Speed Grade Utilization
Logic Elements
Performance (fMAX) Parameter Settings
Stratix II Stratix II GX -4 1,950 200 MHz Contact Northwest Logic
Stratix Stratix GX -5 1,950 200 MHz Contact Northwest Logic
Cyclone II -6 1,950 167 MHz Contact Northwest Logic
Cyclone -6 1,950 133 MHz Contact Northwest Logic

Deliverables

  • Core (Netlist or Source Code)
  • Northwest Logic's Comprehensive Verification Suite (Source Code)
  • Complete Documentation
  • Expert technical Support and Maintenance Updates

Contact Information

For additional information, contact Northwest Logic at:

Northwest Logic, Inc.
1100 Compton Drive., Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
Email: ip@nwlogic.com
URL: www.nwlogic.com/

  Please Give Us Feedback