DDR2 SDRAM Controller
Features
- High-performance access logic with read and write queuing enables the highest possible throughput for all burst length settings (BL4, BL8)
- Pipelined design enables high clock rates with minimal routing constraints
- Bank management logic monitors status of each SDRAM bank (up to 16 banks monitored)—banks only opened or closed when necessary, minimizing access delays
- Half-rate datapath option available, allowing high-rate data throughput with half-rate user interface
- Up to 667 Mb/s/pin data rate on Altera® Stratix® II and Stratix II GX devices
- Optional look-ahead activate, precharge, and auto-precharge logic looks ahead into the user interface queue and examines the access requests, issuing activate, precharge, and auto-precharge commands as soon as possible to maximize memory bandwidth and minimize latency (only available with half-rate datapath versions)
- Supports DDR2 on-die termination (ODT) with fully programmable termination matrices for reads and writes
- Datapath logic specifically optimized for each Altera FPGA family (Stratix II, Stratix II GX, Cyclone® II)
- Run-time configurable timing parameters—CAS latency (CL), additive latency (AL), tRC, tRAS, tRCD, tRP, tMRD, tRRD,tXSNR, tFAW, tWTR, tRTP, tREFC, tRFC, and tWR
- Supports auto-precharge option enabling low random access latencies
- Supports SDRAM self-refresh and power-down modes
- Run-time configurable memory settings (i.e., row bits, column bits, bank bits)
- Automatic generation of initialization and refresh sequences
- 2T timing option for SDRAM address and control signals
- Full support for DDR2 additive latency modes (AL0 - AL5)
- Available with multi-port, front-end option—provides an 8-port interface to the controller with command reordering, extended burst size, and memory test functions
- Optional error correction coding (ECC) and read-modify-write with multi-burst add-on modules available
- Source code license available (VHDL or Verilog HDL)
- Fast response, expert technical support provided by intellectual property (IP) designers
Block Diagram
Figure 1. Northwest Logic DDR2 SDRAM Controller Block Diagram
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Description
Northwest Logic's DDR2 SDRAM controller provides a high-performance interface to DDR2 SDRAM devices. The controller is optimized to achieve high-performance, high-frequency operation with minimal constraints. The controller fully supports DDR2 features such as additive latency and ODT.
The DDR2 SDRAM controller core's local interface is implemented as a queue that enables the local interface to accept a new memory access request every clock as long as the queue is not full. This enables the controller to look ahead into the queue to better optimize throughput and efficiency at the DDR2 memory device interface.
Bank management techniques monitor the status of each DDR2 SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 16 banks can be managed at one time. Access cascading is also supported, allowing read or write requests to be chained together. This results in no delay between requests, enabling up to 100 percent memory throughput for sequential accesses (not including refresh).
The DDR2 SDRAM controller is also available with a half-rate datapath option. This allows high-rate data throughput with a half-rate user interface. The user side data width is twice as wide as the full rate version of the controller to facilitate high bandwidths at the DDR2 pin interface.
A simple local interface is provided for easy integration with other chip logic such as microcontroller buses and FIFO interfaces. The controller is provided with run-time programmable configuration ports for all timing parameters (CAS latency, additive latency, tRC, tRAS, tRCD, tRP, tMRD, tRRD, tXSNR, tFAN, tWTR, tRTP, tREFC, tRFC, and tWR), as well as memory configuration settings. This ensures compatibility with virtually any DDR2 SDRAM configuration.
The DDR2 SDRAM controller core is available with an optional multi-port, front-end module that provides eight user ports into the controller. This module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port, front-end module can perform command reordering to achieve maximum SDRAM bandwidth. The multi-port, front-end module also includes an extended burst interface and a built-in memory test module.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
Deliverables
- Core (Netlist or Source Code)
- Northwest Logic's Comprehensive Verification Suite (Source Code)
- Complete Documentation
- Expert Technical Support and Maintenance Updates
Contact Information
For additional information, contact Northwest Logic, Inc. at:
Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
Email: ip@nwlogic.com
URL: www.nwlogic.com/
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