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Home > Products > Intellectual Property > Interfaces & Peripherals > Memory Controllers > Mobile DDR SDRAM Controller Core Print This Page Subscribe to Email Mobile DDR SDRAM Controller Core from Northwest Logic, Inc. Features High-performance access logic with read and write queuing enables highest possible throughput for all burst length (BL) settings: BL2, BL4, BL8 Pipelined design enables high clock rates with minimal routing constraints Bank management logic monitors status of each SDRAM bank (up to 16 banks monitored)—banks only opened or closed when necessary, minimizing access delays Datapath logic specifically optimized for each Altera® FPGA family (Stratix® II, Stratix II GX, Cyclone® II)  Run-time configurable timing parameters—tCL, tRC, tRCD, tRP, tMRD, tRRD, tREFC Support for auto-precharge option enabling low random access latencies Support for SDRAM self-refresh and power-down modes Support for mobile DDR SDRAM deep power-down and partial array self-refresh modes Run-time configurable timing parameters and memory settings (for example, row bits, column bits, bank bits) Automatic generation of initialization and refresh sequences Support for all standard mobile DDR SDRAM devices Available with multi-port front-end option—provides an eight-port interface to the controller with command reordering, extended burst size, and memory test functions Optional error correction coding (ECC), read-modify-write, and multi-burst add-on modules available Source code license available (VHDL or Verilog) Fast response time and expert technical support provided by experienced Northwest Logic IP designers Block Diagram Figure 1 shows the block diagram for the Northwest Logic Mobile DDR SDRAM Controller Core. Figure 1. Block Diagram for Northwest Logic Mobile DDR SDRAM Controller Core View Larger Size Description The Northwest Logic Mobile DDR SDRAM Controller core provides a high-performance interface to mobile DDR SDRAM devices. The controller is optimized to achieve high-performance, high-frequency operation with minimal constraints. Bank management techniques monitor the status of each mobile DDR SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 16 banks can be managed simultaneously. Access cascading is also supported, enabling read or write requests to be chained together. This bank management technique results in zero delay between requests, enabling up to 100 percent memory throughput for sequential accesses (excluding refresh). The core queues multiple commands, enabling optimal bandwidth utilization. The command queue is also used to perform look-ahead activities, precharges and auto-charges, further improving overall throughput. A simple local interface is provided for easy integration with other device logic, such as microcontroller buses and first-in-first-out (FIFO) interfaces. The controller is provided with run-time programmable configuration ports for all timing parameters (tCL, tRC, tRAS, tRCD, tRP, tMRD, tRRD, tXSNR, tREFC, tRFC, tWR) as well as memory configuration settings. This ensures compatibility with virtually any mobile DDR SDRAM configuration. The Mobile DDR SDRAM Controller core is available with an optional multi-port front-end module, providing eight user ports to the controller. This module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port front-end can perform command reordering to achieve optimal SDRAM bandwidth. The multi-port front-end module also includes an extended burst interface and a built-in memory test module. The Mobile DDR SDRAM Controller core is also available with optional error correction coding (ECC) and read-modify-write modules. Device Utilization and Performance Table 1 shows the typical device utilization results for the DDR SDRAM Controller core. Table 1. Typical Device Utilization for the DDR SDRAM Controller core Supported Altera® Device Speed Grade Logic Cell Utilization Performance (fMAX) Parameter Setting Stratix II / Stratix II GX -4 1950 167 MHz Contact Northwest Logic Cyclone II -6 1950 167 MHz Contact Northwest Logic Deliverables Core (netlist or source code) Northwest Logic's comprehensive Verification Suite (source code) Complete documentation Expert technical support and maintenance updates Contact Information For additional information, contact Northwest Logic at: Northwest Logic, Inc. 1100 Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800, x309 Fax: (503) 533-5900 E-mail: ip@nwlogic.com URL: www.nwlogic.com/ Rate This Page

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