Mobile SDR SDRAM Controller Core

from Northwest Logic, Inc.

Features

• High-performance access logic with read and write queuing enables highest possible throughput for all burst length (BL) settings (BL1, BL2, BL4, BL8)
• Pipelined design enables high clock rates with minimal routing constraints
• Bank management logic monitors status of each SDRAM bank (up to 16 banks monitored), banks only opened or closed when necessary, minimizing access delays
• Run-time configurable timing parameters—t_CL, t_RC, t_RCD, t_RP, t_MRD, t_RRD, and t_REFC
• Support for auto-precharge option enabling low random access latencies
• Support for SDRAM self-refresh and power-down modes
• Support for mobile SDRAM partial array self-refresh, temperature-compensated self-refresh, programmable drive strength, and deep power-down options
• Run-time configurable memory settings (for example, row bits, column bits, bank bits)
• Automatic generation of initialization and refresh sequences
• Support for all standard mobile SDR SDRAM devices
• Available with multi-port front-end module option that provides an eight-port interface to the controller with command reordering, extended burst size, and memory test functions
• Optional error correction coding (ECC), read-modify-write, and multi-burst add-on modules available
• Source code license available (VHDL or Verilog)
• Fast response time and expert technical support provided by experienced Northwest Logic IP designers

Block Diagram

Figure 1 shows the block diagram for the Mobile SDR SDRAM Controller core.

Figure 1. Block Diagram for Northwest Logic Mobile SDR SDRAM Controller Core

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Description

The Northwest Logic Mobile SDR SDRAM Controller core provides a high-performance interface to mobile SDR SDRAM devices. The controller is optimized to achieve high-performance, high-frequency operation with minimal constraints.

Bank management techniques monitor the status of each mobile SDR SDRAM bank. Banks are opened or closed only when necessary, minimizing access delays. Up to 16 banks can be managed simultaneously. Access cascading is also supported, enabling read or write requests to be chained together. This bank management technique results in zero delay between requests, enabling up to 100 percent memory throughput for sequential accesses (excluding refresh).

A simple local interface is provided for easy integration with other device logic such as microcontroller buses and first-in-first-out (FIFO) interfaces. The controller is provided with run-time programmable configuration ports for all timing parameters (t_CL, t_RC, t_RCD, t_RP, t_MRD, t_RRD, t_XSNR, t_REFC, t_RFC, t_WR) as well as memory configuration settings. This ensures compatibility with virtually any mobile SDR SDRAM configuration.

The Mobile SDR SDRAM Controller core is available with an optional multi-port front-end module that provides an eight-port interface to the controller. This module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port front-end module can perform command reordering to achieve optimal SDRAM bandwidth. The multi-port front-end module also includes an extended burst interface and a built-in memory test module.

The Mobile SDR SDRAM Controller core is also available with optional error correction coding (ECC) and read-modify-write modules.

Device Utilization and Performance

Table 1 shows the typical device utilization results for the megafunction.

Deliverables

• Core (netlist or source code)
• Northwest Logic comprehensive Verification Suite (source code)
• Complete documentation
• Expert technical support and maintenance updates

Contact Information

For additional information, contact Northwest Logic, Inc. at:

Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
E-mail: ip@nwlogic.com
URL: www.nwlogic.com/